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fix(plat/st): add UART reset in crash console init

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Add the reset set/clear sequence at the beginning of the function
plat_crash_console_init(). If not done, there is a risk that the UART
is in a bad state and will not be able to print correct characters.

Change-Id: Id31e28773d6c4f26f16d3569d1e3c5aa0e26e039
Signed-off-by: Yann Gautier <yann.gautier@st.com>
This commit is contained in:
Yann Gautier 2020-09-14 17:21:59 +02:00 • committed by Yann Gautier
parent 288f5cf204
commit b38e2ed29e
2 changed files with 16 additions and 1 deletions
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2
plat/st/stm32mp1/stm32mp1_def.h
View file

@ -205,6 +205,8 @@ enum ddr_type {
#define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI
#define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR
#define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN
#define DEBUG_UART_RST_REG RCC_APB1RSTSETR
#define DEBUG_UART_RST_BIT RCC_APB1RSTSETR_UART4RST
/*******************************************************************************
* STM32MP1 ETZPC

15
plat/st/stm32mp1/stm32mp1_helper.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -148,6 +148,19 @@ endfunc plat_my_core_pos
* ---------------------------------------------
*/
func plat_crash_console_init
/* Reset UART peripheral */
ldr r1, =(RCC_BASE + DEBUG_UART_RST_REG)
ldr r2, =DEBUG_UART_RST_BIT
str r2, [r1]
1:
ldr r0, [r1]
ands r2, r0, r2
beq 1b
str r2, [r1, #4] /* RSTCLR register */
2:
ldr r0, [r1]
ands r2, r0, r2
bne 2b
/* Enable GPIOs for UART TX */
ldr r1, =(RCC_BASE + DEBUG_UART_TX_GPIO_BANK_CLK_REG)
ldr r2, [r1]