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Merge changes I5d7e3cf3,Ie81f2fc5,If869ac93,I2cf2badf,Ic291eb13 into integration

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* changes:
  fix(sptool): add leading zeroes in UUID conversion
  feat(tc): enable SMMU for DPU
  feat(tc): add reserved memory region for Gralloc
  feat(tc): enable GPU
  fix(tc): remove the bootargs node
This commit is contained in:
Manish Pandey 2022-02-02 18:41:08 +01:00 • committed by TrustedFirmware Code Review
commit b350811cc9
2 changed files with 32 additions and 3 deletions
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31
fdts/tc.dts
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@ -17,7 +17,6 @@
}; };
chosen { chosen {
bootargs = "console=ttyAMA0 debug user_debug=31 earlycon=pl011,0x7ff80000 loglevel=9 androidboot.hardware=total_compute androidboot.boot_devices=1c050000.mmci ip=dhcp androidboot.selinux=permissive allow_mismatched_32bit_el0";
stdout-path = "serial0:115200n8"; stdout-path = "serial0:115200n8";
}; };
@ -207,6 +206,13 @@
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
linux,cma-default;
};
optee@0xfce00000 { optee@0xfce00000 {
reg = <0x00000000 0xfce00000 0 0x00200000>; reg = <0x00000000 0xfce00000 0 0x00200000>;
no-map; no-map;
@ -435,6 +441,26 @@
clock-names = "mclk", "apb_pclk"; clock-names = "mclk", "apb_pclk";
}; };
gpu: gpu@2d000000 {
compatible = "arm,mali-midgard";
reg = <0x0 0x2d000000 0x0 0x200000>;
interrupts = <0 66 4>, <0 67 4>, <0 65 4>;
interrupt-names = "JOB", "MMU", "GPU";
clocks = <&soc_refclk100mhz>;
clock-names = "clk_mali";
operating-points = <
/* KHz uV */
50000 820000
>;
};
smmu: smmu@2ce00000 {
#iommu-cells = <1>;
compatible = "arm,smmu-v3";
reg = <0x0 0x2ce00000 0x0 0x20000>;
status = "okay";
};
dp0: display@2cc00000 { dp0: display@2cc00000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -444,6 +470,9 @@
interrupt-names = "DPU"; interrupt-names = "DPU";
clocks = <&scmi_clk 0>; clocks = <&scmi_clk 0>;
clock-names = "aclk"; clock-names = "aclk";
iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>,
<&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>,
<&smmu 8>, <&smmu 9>;
pl0: pipeline@0 { pl0: pipeline@0 {
reg = <0>; reg = <0>;
clocks = <&scmi_clk 1>; clocks = <&scmi_clk 1>;

4
tools/sptool/sp_mk_generator.py
View file

@ -1,5 +1,5 @@
#!/usr/bin/python3 #!/usr/bin/python3
# Copyright (c) 2020-2021, Arm Limited. All rights reserved. # Copyright (c) 2020-2022, Arm Limited. All rights reserved.
# #
# SPDX-License-Identifier: BSD-3-Clause # SPDX-License-Identifier: BSD-3-Clause
@ -134,7 +134,7 @@ with open(gen_file, 'w') as out_file:
int.from_bytes(y[1], byteorder='little', signed=False), int.from_bytes(y[1], byteorder='little', signed=False),
int.from_bytes(y[2], byteorder='little', signed=False), int.from_bytes(y[2], byteorder='little', signed=False),
int.from_bytes(y[3], byteorder='little', signed=False)) int.from_bytes(y[3], byteorder='little', signed=False))
uuid_std = uuid.UUID(f'{z[0]:04x}{z[1]:04x}{z[2]:04x}{z[3]:04x}') uuid_std = uuid.UUID(f'{z[0]:08x}{z[1]:08x}{z[2]:08x}{z[3]:08x}')
""" """
Append FIP_ARGS Append FIP_ARGS