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Merge "fix(xilinx): check proc variable before use" into integration

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Joanna Farley 2024-05-02 09:28:03 +02:00 • committed by TrustedFirmware Code Review
commit b109b00669
3 changed files with 45 additions and 2 deletions
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17
plat/xilinx/versal/plat_psci.c
View file

@ -1,6 +1,6 @@
/*
* Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
* Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -36,6 +36,9 @@ static int32_t versal_pwr_domain_on(u_register_t mpidr)
}
proc = pm_get_proc((uint32_t)cpu_id);
if (!proc) {
return PSCI_E_INTERN_FAIL;
}
/* Send request to PMC to wake up selected ACPU core */
(void)pm_req_wakeup(proc->node_id, (versal_sec_entry & 0xFFFFFFFFU) | 0x1U,
@ -59,6 +62,10 @@ static void versal_pwr_domain_suspend(const psci_power_state_t *target_state)
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
if (!proc) {
return;
}
for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
@ -96,6 +103,10 @@ static void versal_pwr_domain_suspend_finish(
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
if (!proc) {
return;
}
for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
@ -190,6 +201,10 @@ static void versal_pwr_domain_off(const psci_power_state_t *target_state)
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
if (!proc) {
return;
}
for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);

12
plat/xilinx/versal_net/plat_psci_pm.c
View file

@ -63,6 +63,10 @@ static void versal_net_pwr_domain_off(const psci_power_state_t *target_state)
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
if (!proc) {
return;
}
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
@ -143,6 +147,10 @@ static void versal_net_pwr_domain_suspend(const psci_power_state_t *target_state
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
if (!proc) {
return;
}
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
@ -186,6 +194,10 @@ static void versal_net_pwr_domain_suspend_finish(const psci_power_state_t *targe
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
if (!proc) {
return;
}
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);

18
plat/xilinx/zynqmp/plat_psci.c
View file

@ -1,6 +1,6 @@
/*
* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
* Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -42,7 +42,11 @@ static int32_t zynqmp_pwr_domain_on(u_register_t mpidr)
if (cpu_id == -1) {
return PSCI_E_INTERN_FAIL;
}
proc = pm_get_proc(cpu_id);
if (!proc) {
return PSCI_E_INTERN_FAIL;
}
/* Check the APU proc status before wakeup */
ret = pm_get_node_status(proc->node_id, buff);
@ -64,6 +68,10 @@ static void zynqmp_pwr_domain_off(const psci_power_state_t *target_state)
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
if (!proc) {
return;
}
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
@ -89,6 +97,10 @@ static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state)
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
if (!proc) {
return;
}
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
@ -121,6 +133,10 @@ static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_st
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
if (!proc) {
return;
}
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);