From b0d441bdadae3b38e3a670e03341603785b39f3c Mon Sep 17 00:00:00 2001 From: Sona Mathew Date: Tue, 21 May 2024 14:03:11 -0500 Subject: [PATCH] fix(cpus): workaround for CVE-2024-5660 for Cortex-X3 Implements mitigation for CVE-2024-5660 that affects Cortex-X3 revisions r0p0, r1p0, r1p1, r1p2. The workaround is to disable the hardware page aggregation at EL3 by setting CPUECTLR_EL1[46] = 1'b1. Public Documentation: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-5660 Change-Id: Ibe90313948102ece3469f2cfe3faccc7f4beeabe Signed-off-by: Sona Mathew --- lib/cpus/aarch64/cortex_x3.S | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S index a81c4cf93..6becf7b2e 100644 --- a/lib/cpus/aarch64/cortex_x3.S +++ b/lib/cpus/aarch64/cortex_x3.S @@ -26,6 +26,13 @@ wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3 #endif /* WORKAROUND_CVE_2022_23960 */ +/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ +workaround_reset_start cortex_x3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 + sysreg_bit_set CORTEX_X3_CPUECTLR_EL1, BIT(46) +workaround_reset_end cortex_x3, CVE(2024, 5660) + +check_erratum_ls cortex_x3, CVE(2024, 5660), CPU_REV(1, 2) + workaround_reset_start cortex_x3, ERRATUM(2070301), ERRATA_X3_2070301 sysreg_bitfield_insert CORTEX_X3_CPUECTLR2_EL1, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV, \ CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH