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fix(versal2): correct the UFS clock rates

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Update the UFS clock rates as per the expected range
- Update the clock rates of "ufs_phy_clk" and "ufs_ref_pclk" to 26MHz
as 100MHz is not the valid clock rate for these two clocks.
- cpu_clock rate (908KHz) is not valid clock for UFS, hence skip setting
up UFS clocks to cpu_clock for SPP platform.

Change-Id: I31863619ca1bd527df283d1636493dd8fce18809
Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
This commit is contained in:
Sai Krishna Potthuri 2024-10-04 11:41:58 +05:30 • committed by Amit Nagal
parent 607ab7ae2f
commit b048601eee
1 changed files with 7 additions and 2 deletions
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9
plat/amd/versal2/scmi.c
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@ -51,8 +51,8 @@ static struct scmi_clk scmi0_clock[] = {
CLOCK_CELL(CLK_SERIAL1_0, CLK_SERIAL1_0, "uart1_uartclk", true, 100000000), CLOCK_CELL(CLK_SERIAL1_0, CLK_SERIAL1_0, "uart1_uartclk", true, 100000000),
CLOCK_CELL(CLK_SERIAL1_1, CLK_SERIAL1_1, "uart1_apb_pclk", true, 100000000), CLOCK_CELL(CLK_SERIAL1_1, CLK_SERIAL1_1, "uart1_apb_pclk", true, 100000000),
CLOCK_CELL(CLK_UFS0_0, CLK_UFS0_0, "ufs_core_clk", true, 100000000), CLOCK_CELL(CLK_UFS0_0, CLK_UFS0_0, "ufs_core_clk", true, 100000000),
CLOCK_CELL(CLK_UFS0_1, CLK_UFS0_1, "ufs_phy_clk", true, 100000000), CLOCK_CELL(CLK_UFS0_1, CLK_UFS0_1, "ufs_phy_clk", true, 26000000),
CLOCK_CELL(CLK_UFS0_2, CLK_UFS0_2, "ufs_ref_pclk", true, 100000000), CLOCK_CELL(CLK_UFS0_2, CLK_UFS0_2, "ufs_ref_pclk", true, 26000000),
CLOCK_CELL(CLK_USB0_0, CLK_USB0_0, "usb0_bus_clk", true, 100000000), CLOCK_CELL(CLK_USB0_0, CLK_USB0_0, "usb0_bus_clk", true, 100000000),
CLOCK_CELL(CLK_USB0_1, CLK_USB0_1, "usb0_ref_clk", true, 100000000), CLOCK_CELL(CLK_USB0_1, CLK_USB0_1, "usb0_ref_clk", true, 100000000),
CLOCK_CELL(CLK_USB0_2, CLK_USB0_2, "usb0_dwc_clk", true, 100000000), CLOCK_CELL(CLK_USB0_2, CLK_USB0_2, "usb0_dwc_clk", true, 100000000),
@ -649,6 +649,11 @@ void init_scmi_server(void)
/* Keep i2c on 100MHz to calculate rates properly */ /* Keep i2c on 100MHz to calculate rates properly */
if (i >= CLK_I2C0_0 && i <= CLK_I2C7_0) if (i >= CLK_I2C0_0 && i <= CLK_I2C7_0)
continue; continue;
/* Keep UFS clocks to default values to get the expected rates */
if (i >= CLK_UFS0_0 && i <= CLK_UFS0_2)
continue;
/* /*
* SPP supports multiple versions. * SPP supports multiple versions.
* The cpu_clock value is set to corresponding SPP * The cpu_clock value is set to corresponding SPP