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fix(cpus): workaround for Cortex-X2 erratum 2778471

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Cortex-X2 erratum 2778471 is a Cat B erratum that applies
to revisions r0p1, r1p0, r2p0 and r2p1 and is still open.
The workaround is to set CPUACTLR3_EL1[47] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: Ia95f0e276482283bf50e06c58c2bc5faab3f62c6
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
This commit is contained in:
Sona Mathew 2023-12-09 13:09:30 -06:00
parent c9508d6a10
commit b01a93d778
5 changed files with 22 additions and 2 deletions
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4
docs/design/cpu-specific-build-macros.rst
View file

@ -761,6 +761,10 @@ For Cortex-X2, the following errata build flags are defined :
CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
CPU and is still open.
- ``ERRATA_X2_2778471``: This applies errata 2778471 workaround to Cortex-X2
CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
CPU and it is still open.
For Cortex-X3, the following errata build flags are defined :
- ``ERRATA_X3_2070301``: This applies errata 2070301 workaround to the Cortex-X3

7
include/lib/cpus/aarch64/cortex_x2.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -27,6 +27,11 @@
#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9)
/*******************************************************************************
* CPU Auxiliary Control register 3 specific definitions.
******************************************************************************/
#define CORTEX_X2_CPUACTLR3_EL1 S3_0_C15_C1_2
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/

6
lib/cpus/aarch64/cortex_x2.S
View file

@ -133,6 +133,12 @@ workaround_reset_end cortex_x2, ERRATUM(2768515)
check_erratum_ls cortex_x2, ERRATUM(2768515), CPU_REV(2, 1)
workaround_reset_start cortex_x2, ERRATUM(2778471), ERRATA_X2_2778471
sysreg_bit_set CORTEX_X2_CPUACTLR3_EL1, BIT(47)
workaround_reset_end cortex_x2, ERRATUM(2778471)
check_erratum_ls cortex_x2, ERRATUM(2778471), CPU_REV(2, 1)
workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*

4
lib/cpus/cpu-ops.mk
View file

@ -765,6 +765,10 @@ CPU_FLAG_LIST += ERRATA_X2_2742423
# still open.
CPU_FLAG_LIST += ERRATA_X2_2768515
# Flag to apply erratum 2778471 workaround during reset. This erratum applies
# to revisions r0p0, r1p0, r2p0, r2p1 of the Cortex-X2 cpu and it is still open.
CPU_FLAG_LIST += ERRATA_X2_2778471
# Flag to apply erratum 2070301 workaround on reset. This erratum applies
# to revisions r0p0, r1p0, r1p1 and r1p2 of the Cortex-X3 cpu and is
# still open.

3
services/std_svc/errata_abi/errata_abi_main.c
View file

@ -385,7 +385,8 @@ struct em_cpu_list cpu_list[] = {
ERRATA_NON_ARM_INTERCONNECT},
[10] = {2742423, 0x00, 0x21, ERRATA_X2_2742423},
[11] = {2768515, 0x00, 0x21, ERRATA_X2_2768515},
[12 ... ERRATA_LIST_END] = UNDEF_ERRATA,
[12] = {2778471, 0x00, 0x21, ERRATA_X2_2778471},
[13 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* CORTEX_X2_H_INC */