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fix(cpus): workaround for Neoverse V2 erratum 2719105

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Neoverse V2 erratum 2719105 is a Cat B erratum that applies to all
revisions <= r0p1 and is fixed in r0p2.

The erratum is avoided by setting CPUACTLR2_EL1[0] to 1 to force
PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations
to other PE caches. There might be a small performance degradation
to this workaround for certain workloads that share data.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Id026edcb7ee1ca93371ce0001d18f5a8282c49ba
This commit is contained in:
Bipin Ravi 2023-09-18 17:27:29 -05:00
parent 8852fb5b7d
commit b01140256b
5 changed files with 23 additions and 2 deletions
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4
docs/design/cpu-specific-build-macros.rst
View file

@ -532,6 +532,10 @@ For Neoverse V2, the following errata build flags are defined :
IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed
in r0p2. in r0p2.
- ``ERRATA_V2_2719105``: This applies errata 2719105 workaround to Neoverse-V2
CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
r0p2.
- ``ERRATA_V2_2801372``: This applies errata 2801372 workaround to Neoverse-V2 - ``ERRATA_V2_2801372``: This applies errata 2801372 workaround to Neoverse-V2
CPU, this affects all configurations. This needs to be enabled for revisions CPU, this affects all configurations. This needs to be enabled for revisions
r0p0 and r0p1. It has been fixed in r0p2. r0p0 and r0p1. It has been fixed in r0p2.

6
include/lib/cpus/aarch64/neoverse_v2.h
View file

@ -31,4 +31,10 @@
#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB U(11) #define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB U(11)
#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) #define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
/*******************************************************************************
* CPU Auxiliary Control register 2 specific definitions.
******************************************************************************/
#define NEOVERSE_V2_CPUACTLR2_EL1 S3_0_C15_C1_1
#define NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
#endif /* NEOVERSE_V2_H */ #endif /* NEOVERSE_V2_H */

6
lib/cpus/aarch64/neoverse_v2.S
View file

@ -29,6 +29,12 @@ workaround_reset_end neoverse_v2, ERRATUM(2331132)
check_erratum_ls neoverse_v2, ERRATUM(2331132), CPU_REV(0, 2) check_erratum_ls neoverse_v2, ERRATUM(2331132), CPU_REV(0, 2)
workaround_reset_start neoverse_v2, ERRATUM(2719105), ERRATA_V2_2719105
sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, NEOVERSE_V2_CPUACTLR2_EL1_BIT_0
workaround_reset_end neoverse_v2, ERRATUM(2719105)
check_erratum_ls neoverse_v2, ERRATUM(2719105), CPU_REV(0, 1)
workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
/* dsb before isb of power down sequence */ /* dsb before isb of power down sequence */
dsb sy dsb sy

4
lib/cpus/cpu-ops.mk
View file

@ -794,6 +794,10 @@ CPU_FLAG_LIST += ERRATA_V2_2331132
# erratum applies to revisions r0p0, rop1. Fixed in r0p2. # erratum applies to revisions r0p0, rop1. Fixed in r0p2.
CPU_FLAG_LIST += ERRATA_V2_2719103 CPU_FLAG_LIST += ERRATA_V2_2719103
# Flag to apply erratum 2719105 workaround during reset. This erratum applies
# to revisions r0p0 and r0p1. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_V2_2719105
# Flag to apply erratum 2801372 workaround for all configurations. # Flag to apply erratum 2801372 workaround for all configurations.
# This erratum applies to revisions r0p0, r0p1. Fixed in r0p2. # This erratum applies to revisions r0p0, r0p1. Fixed in r0p2.
CPU_FLAG_LIST += ERRATA_V2_2801372 CPU_FLAG_LIST += ERRATA_V2_2801372

5
services/std_svc/errata_abi/errata_abi_main.c
View file

@ -402,8 +402,9 @@ struct em_cpu_list cpu_list[] = {
[0] = {2331132, 0x00, 0x02, ERRATA_V2_2331132}, [0] = {2331132, 0x00, 0x02, ERRATA_V2_2331132},
[1] = {2719103, 0x00, 0x01, ERRATA_V2_2719103, \ [1] = {2719103, 0x00, 0x01, ERRATA_V2_2719103, \
ERRATA_NON_ARM_INTERCONNECT}, ERRATA_NON_ARM_INTERCONNECT},
[2] = {2801372, 0x00, 0x01, ERRATA_V2_2801372}, [2] = {2719105, 0x00, 0x01, ERRATA_V2_2719105},
[3 ... ERRATA_LIST_END] = UNDEF_ERRATA, [3] = {2801372, 0x00, 0x01, ERRATA_V2_2801372},
[4 ... ERRATA_LIST_END] = UNDEF_ERRATA,
} }
}, },
#endif /* NEOVERSE_V2_H_INC */ #endif /* NEOVERSE_V2_H_INC */