errata: workaround for Cortex-A710 erratum 2017096

Cortex-A710 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0 and is still open. The workaround is to
set CPUECLTR_EL1[8] to 1 which disables store issue prefetching.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: If5f61ec30dbc2fab7f2c68663996057086e374e3

docs/design/cpu-specific-build-macros.rst

@@ -382,6 +382,11 @@ For Cortex-A710, the following errata build flags are defined :
    Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU
    and is still open.
 
+-  ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to
+   Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
+   of the CPU and is still open.
+
+
 For Neoverse N2, the following errata build flags are defined :
 
 -  ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2

include/lib/cpus/aarch64/cortex_a710.h

@@ -13,6 +13,7 @@
  * CPU Extended Control register specific definitions
  ******************************************************************************/
 #define CORTEX_A710_CPUECTLR_EL1				S3_0_C15_C1_4
+#define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT                   (ULL(1) << 8)
 
 /*******************************************************************************
  * CPU Power Control register specific definitions

lib/cpus/aarch64/cortex_a710.S

@@ -133,6 +133,33 @@ func check_errata_2055002
 	b	cpu_rev_var_ls
 endfunc check_errata_2055002
 
+/* -------------------------------------------------------------
+ * Errata Workaround for Cortex-A710 Erratum 2017096.
+ * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * -------------------------------------------------------------
+ */
+func errata_a710_2017096_wa
+	/* Compare x0 against revision r0p0 to r2p0 */
+	mov     x17, x30
+	bl      check_errata_2017096
+	cbz     x0, 1f
+	mrs     x1, CORTEX_A710_CPUECTLR_EL1
+	orr     x1, x1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT
+	msr     CORTEX_A710_CPUECTLR_EL1, x1
+
+1:
+	ret     x17
+endfunc errata_a710_2017096_wa
+
+func check_errata_2017096
+	/* Applies to r0p0, r1p0, r2p0 */
+	mov     x1, #0x20
+	b       cpu_rev_var_ls
+endfunc check_errata_2017096
+
 	/* ----------------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ----------------------------------------------------
@@ -166,6 +193,7 @@ func cortex_a710_errata_report
 	report_errata ERRATA_A710_1987031, cortex_a710, 1987031
 	report_errata ERRATA_A710_2081180, cortex_a710, 2081180
 	report_errata ERRATA_A710_2055002, cortex_a710, 2055002
+	report_errata ERRATA_A710_2017096, cortex_a710, 2017096
 
 	ldp	x8, x30, [sp], #16
 	ret
@@ -196,6 +224,10 @@ func cortex_a710_reset_func
 	bl	errata_a710_2055002_wa
 #endif
 
+#if ERRATA_A710_2017096
+	mov     x0, x18
+	bl      errata_a710_2017096_wa
+#endif
 	isb
 	ret	x19
 endfunc cortex_a710_reset_func

lib/cpus/cpu-ops.mk

@@ -433,6 +433,10 @@ ERRATA_N2_2025414	?=0
 # to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open.
 ERRATA_A710_2055002	?=0
 
+# Flag to apply erratum 2017096 workaround during reset. This erratum applies
+# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
+ERRATA_A710_2017096	?=0
+
 # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
 # Applying the workaround results in higher DSU power consumption on idle.
 ERRATA_DSU_798953	?=0
@@ -798,6 +802,10 @@ $(eval $(call add_define,ERRATA_N2_2025414))
 $(eval $(call assert_boolean,ERRATA_A710_2055002))
 $(eval $(call add_define,ERRATA_A710_2055002))
 
+# Process ERRATA_A710_2017096 flag
+$(eval $(call assert_boolean,ERRATA_A710_2017096))
+$(eval $(call add_define,ERRATA_A710_2017096))
+
 # Process ERRATA_DSU_798953 flag
 $(eval $(call assert_boolean,ERRATA_DSU_798953))
 $(eval $(call add_define,ERRATA_DSU_798953))