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feat(st-crypto): add STM32 RNG driver
This driver manages the STM32 Random Number Generator peripheral. Change-Id: I4403ebb2dbdaa8df993a4413f1ef48eeba00427c Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
This commit is contained in:
Yann Gautier
Lionel Debieve
parent
4bb4e83649
commit
af8dee20d5
2 changed files with 284 additions and 0 deletions
269
drivers/st/crypto/stm32_rng.c
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269
drivers/st/crypto/stm32_rng.c
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/*
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* Copyright (c) 2022, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <stdbool.h>
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#include <arch_helpers.h>
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#include <drivers/clk.h>
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#include <drivers/delay_timer.h>
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#include <drivers/st/stm32_rng.h>
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#include <drivers/st/stm32mp_reset.h>
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#include <lib/mmio.h>
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#include <libfdt.h>
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#include <platform_def.h>
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#if STM32_RNG_VER == 2
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#define DT_RNG_COMPAT "st,stm32-rng"
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#endif
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#if STM32_RNG_VER == 4
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#define DT_RNG_COMPAT "st,stm32mp13-rng"
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#endif
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#define RNG_CR 0x00U
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#define RNG_SR 0x04U
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#define RNG_DR 0x08U
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#define RNG_CR_RNGEN BIT(2)
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#define RNG_CR_IE BIT(3)
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#define RNG_CR_CED BIT(5)
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#define RNG_CR_CLKDIV GENMASK(19, 16)
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#define RNG_CR_CLKDIV_SHIFT 16U
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#define RNG_CR_CONDRST BIT(30)
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#define RNG_SR_DRDY BIT(0)
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#define RNG_SR_CECS BIT(1)
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#define RNG_SR_SECS BIT(2)
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#define RNG_SR_CEIS BIT(5)
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#define RNG_SR_SEIS BIT(6)
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#define RNG_TIMEOUT_US 100000U
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#define RNG_TIMEOUT_STEP_US 10U
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#define TIMEOUT_US_1MS 1000U
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#define RNG_NIST_CONFIG_A 0x00F40F00U
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#define RNG_NIST_CONFIG_B 0x01801000U
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#define RNG_NIST_CONFIG_C 0x00F00D00U
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#define RNG_NIST_CONFIG_MASK GENMASK(25, 8)
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#define RNG_MAX_NOISE_CLK_FREQ 48000000U
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struct stm32_rng_instance {
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uintptr_t base;
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unsigned long clock;
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};
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static struct stm32_rng_instance stm32_rng;
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static void seed_error_recovery(void)
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{
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uint8_t i __maybe_unused;
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/* Recommended by the SoC reference manual */
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mmio_clrbits_32(stm32_rng.base + RNG_SR, RNG_SR_SEIS);
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dmbsy();
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#if STM32_RNG_VER == 2
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/* No Auto-reset on version 2, need to clean FIFO */
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for (i = 12U; i != 0U; i--) {
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(void)mmio_read_32(stm32_rng.base + RNG_DR);
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}
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dmbsy();
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#endif
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if ((mmio_read_32(stm32_rng.base + RNG_SR) & RNG_SR_SEIS) != 0U) {
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ERROR("RNG noise\n");
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panic();
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}
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}
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static uint32_t stm32_rng_clock_freq_restrain(void)
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{
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unsigned long clock_rate;
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uint32_t clock_div = 0U;
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clock_rate = clk_get_rate(stm32_rng.clock);
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/*
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* Get the exponent to apply on the CLKDIV field in RNG_CR register
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* No need to handle the case when clock-div > 0xF as it is physically
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* impossible
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*/
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while ((clock_rate >> clock_div) > RNG_MAX_NOISE_CLK_FREQ) {
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clock_div++;
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}
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VERBOSE("RNG clk rate : %lu\n", clk_get_rate(stm32_rng.clock) >> clock_div);
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return clock_div;
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}
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static int stm32_rng_enable(void)
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{
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uint32_t sr;
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uint64_t timeout;
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uint32_t clock_div __maybe_unused;
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#if STM32_RNG_VER == 2
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mmio_write_32(stm32_rng.base + RNG_CR, RNG_CR_RNGEN | RNG_CR_CED);
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#endif
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#if STM32_RNG_VER == 4
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/* Reset internal block and disable CED bit */
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clock_div = stm32_rng_clock_freq_restrain();
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/* Update configuration fields */
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mmio_clrsetbits_32(stm32_rng.base + RNG_CR, RNG_NIST_CONFIG_MASK,
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RNG_NIST_CONFIG_A | RNG_CR_CONDRST | RNG_CR_CED);
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mmio_clrsetbits_32(stm32_rng.base + RNG_CR, RNG_CR_CLKDIV,
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(clock_div << RNG_CR_CLKDIV_SHIFT));
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mmio_clrsetbits_32(stm32_rng.base + RNG_CR, RNG_CR_CONDRST, RNG_CR_RNGEN);
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#endif
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timeout = timeout_init_us(RNG_TIMEOUT_US);
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sr = mmio_read_32(stm32_rng.base + RNG_SR);
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while ((sr & RNG_SR_DRDY) == 0U) {
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if (timeout_elapsed(timeout)) {
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WARN("Timeout waiting\n");
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return -ETIMEDOUT;
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}
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if ((sr & (RNG_SR_SECS | RNG_SR_SEIS)) != 0U) {
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seed_error_recovery();
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timeout = timeout_init_us(RNG_TIMEOUT_US);
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}
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udelay(RNG_TIMEOUT_STEP_US);
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sr = mmio_read_32(stm32_rng.base + RNG_SR);
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}
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VERBOSE("Init RNG done\n");
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return 0;
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}
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/*
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* stm32_rng_read - Read a number of random bytes from RNG
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* out: pointer to the output buffer
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* size: number of bytes to be read
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* Return 0 on success, non-0 on failure
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*/
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int stm32_rng_read(uint8_t *out, uint32_t size)
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{
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uint8_t *buf = out;
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size_t len = size;
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int nb_tries;
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uint32_t data32;
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int rc = 0;
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unsigned int count;
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if (stm32_rng.base == 0U) {
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return -EPERM;
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}
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while (len != 0U) {
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nb_tries = RNG_TIMEOUT_US / RNG_TIMEOUT_STEP_US;
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do {
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uint32_t status = mmio_read_32(stm32_rng.base + RNG_SR);
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if ((status & (RNG_SR_SECS | RNG_SR_SEIS)) != 0U) {
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seed_error_recovery();
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}
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udelay(RNG_TIMEOUT_STEP_US);
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nb_tries--;
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if (nb_tries == 0) {
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rc = -ETIMEDOUT;
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goto bail;
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}
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} while ((mmio_read_32(stm32_rng.base + RNG_SR) &
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RNG_SR_DRDY) == 0U);
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count = 4U;
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while (len != 0U) {
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data32 = mmio_read_32(stm32_rng.base + RNG_DR);
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count--;
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memcpy(buf, &data32, MIN(len, sizeof(uint32_t)));
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buf += MIN(len, sizeof(uint32_t));
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len -= MIN(len, sizeof(uint32_t));
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if (count == 0U) {
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break;
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}
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}
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}
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bail:
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if (rc != 0) {
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memset(out, 0, buf - out);
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}
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return rc;
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}
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/*
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* stm32_rng_init: Initialize rng from DT
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* return 0 on success, negative value on failure
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*/
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int stm32_rng_init(void)
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{
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void *fdt;
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struct dt_node_info dt_rng;
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int node;
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if (stm32_rng.base != 0U) {
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/* Driver is already initialized */
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return 0;
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}
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if (fdt_get_address(&fdt) == 0) {
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panic();
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}
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node = dt_get_node(&dt_rng, -1, DT_RNG_COMPAT);
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if (node < 0) {
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return 0;
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}
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if (dt_rng.status == DT_DISABLED) {
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return 0;
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}
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assert(dt_rng.base != 0U);
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stm32_rng.base = dt_rng.base;
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if (dt_rng.clock < 0) {
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panic();
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}
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stm32_rng.clock = (unsigned long)dt_rng.clock;
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clk_enable(stm32_rng.clock);
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if (dt_rng.reset >= 0) {
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int ret;
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ret = stm32mp_reset_assert((unsigned long)dt_rng.reset,
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TIMEOUT_US_1MS);
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if (ret != 0) {
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panic();
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}
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udelay(20);
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ret = stm32mp_reset_deassert((unsigned long)dt_rng.reset,
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TIMEOUT_US_1MS);
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if (ret != 0) {
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panic();
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}
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}
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return stm32_rng_enable();
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}
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15
include/drivers/st/stm32_rng.h
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15
include/drivers/st/stm32_rng.h
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@ -0,0 +1,15 @@
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/*
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* Copyright (c) 2022, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef STM32_RNG_H
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#define STM32_RNG_H
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#include <stdint.h>
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int stm32_rng_read(uint8_t *out, uint32_t size);
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int stm32_rng_init(void);
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#endif /* STM32_RNG_H */
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