fix(cpus): workaround for Cortex-A510 erratum 2684597

Cortex-A510 erratum 2684597 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. The
workaround is to execute a TSB CSYNC and DSB before executing WFI for
power down.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1873361/latest
https://developer.arm.com/documentation/SDEN1873351/latest

Change-Id: Ic0b24b600bc013eb59c797401fbdc9bda8058d6d
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

docs/design/cpu-specific-build-macros.rst

@@ -673,6 +673,10 @@ For Cortex-A510, the following errata build flags are defined :
    Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2,
    r0p3, r1p0, r1p1. It is fixed in r1p2.
 
+-  ``ERRATA_A510_2684597``: This applies erratum 2684597 workaround to
+   Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2,
+   r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3.
+
 DSU Errata Workarounds
 ----------------------
 

lib/cpus/aarch64/cortex_a510.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -361,6 +361,45 @@ func check_errata_2666669
 	b	cpu_rev_var_ls
 endfunc check_errata_2666669
 
+/* ------------------------------------------------------
+ * Errata Workaround for Cortex-A510 Erratum 2684597.
+ * This erratum applies to revision r0p0, r0p1, r0p2,
+ * r0p3, r1p0, r1p1 and r1p2 of the Cortex-A510 cpu and
+ * is fixed in r1p3.
+ * Shall clobber: x0-x17
+ * ------------------------------------------------------
+ */
+	.globl	errata_cortex_a510_2684597_wa
+func errata_cortex_a510_2684597_wa
+	mov	x17, x30
+	/* Ensure this errata is only applied to Cortex-A510 cores */
+	jump_if_cpu_midr	CORTEX_A510_MIDR,	1f
+	b	2f
+
+1:
+	/* Check workaround compatibility. */
+	mov	x0, x18
+	bl	check_errata_2684597
+	cbz	x0, 2f
+
+	tsb	csync
+2:
+	ret	x17
+endfunc errata_cortex_a510_2684597_wa
+/* ------------------------------------------------------
+ * Errata Workaround for Cortex-A510 Erratum 2684597.
+ * This erratum applies to revision r0p0, r0p1, r0p2,
+ * r0p3, r1p0, r1p1 and r1p2 of the Cortex-A510 cpu and
+ * is fixed in r1p3.
+ * Shall clobber: x0-x17
+ * ------------------------------------------------------
+ */
+func check_errata_2684597
+	/* Applies to revision < r1p3 */
+	mov	x1, #0x12
+	b	cpu_rev_var_ls
+endfunc check_errata_2684597
+
 	/* ----------------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ----------------------------------------------------
@@ -401,6 +440,7 @@ func cortex_a510_errata_report
 	report_errata ERRATA_A510_2347730, cortex_a510, 2347730
 	report_errata ERRATA_A510_2371937, cortex_a510, 2371937
 	report_errata ERRATA_A510_2666669, cortex_a510, 2666669
+	report_errata ERRATA_A510_2684597, cortex_a510, 2684597
 	report_errata ERRATA_DSU_2313941, cortex_a510, dsu_2313941
 
 	ldp	x8, x30, [sp], #16

lib/cpus/aarch64/runtime_errata.S

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm_macros.S>
+#include <cortex_a510.h>
+#include <cpu_macros.S>
+
+/*
+ * void apply_cpu_pwr_dwn_errata(void);
+ *
+ * This function applies various CPU errata during power down.
+ */
+	.globl apply_cpu_pwr_dwn_errata
+func apply_cpu_pwr_dwn_errata
+	mov	x19, x30
+	bl      cpu_get_rev_var
+	mov	x18, x0
+
+#if ERRATA_A510_2684597
+	bl errata_cortex_a510_2684597_wa
+#endif
+
+	ret	x19
+endfunc apply_cpu_pwr_dwn_errata

lib/cpus/cpu-ops.mk

@@ -736,6 +736,11 @@ ERRATA_A510_2371937	?=0
 # to revisions r0p0, r0p1, r0p2, r0p3, r1p0, and r1p1. It is fixed in r1p2.
 ERRATA_A510_2666669	?=0
 
+# Flag to apply erratum 2684597 workaround during powerdown. This erratum
+# applies to revision r0p0, r0p1, r0p2, r0p3, r1p0, r1p1 and r1p2 of the
+# Cortex-A510 cpu and is fixed in r1p3.
+ERRATA_A510_2684597	?=0
+
 # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
 # Applying the workaround results in higher DSU power consumption on idle.
 ERRATA_DSU_798953	?=0
@@ -1390,6 +1395,10 @@ $(eval $(call add_define,ERRATA_A510_2371937))
 $(eval $(call assert_boolean,ERRATA_A510_2666669))
 $(eval $(call add_define,ERRATA_A510_2666669))
 
+# Process ERRATA_A510_2684597 flag
+$(eval $(call assert_boolean,ERRATA_A510_2684597))
+$(eval $(call add_define,ERRATA_A510_2684597))
+
 #Process ERRATA_DSU_798953 flag
 $(eval $(call assert_boolean,ERRATA_DSU_798953))
 $(eval $(call add_define,ERRATA_DSU_798953))

lib/psci/aarch64/psci_helpers.S

@@ -124,6 +124,9 @@ endfunc psci_do_pwrup_cache_maintenance
  * -----------------------------------------------------------------------
  */
 func psci_power_down_wfi
+#if ERRATA_A510_2684597
+	bl apply_cpu_pwr_dwn_errata
+#endif
 	dsb	sy		// ensure write buffer empty
 1:
 	wfi

lib/psci/psci_lib.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -21,7 +21,8 @@ PSCI_LIB_SOURCES	:=	lib/el3_runtime/cpu_data_array.c	\
 				lib/psci/${ARCH}/psci_helpers.S
 
 ifeq (${ARCH}, aarch64)
-PSCI_LIB_SOURCES	+=	lib/el3_runtime/aarch64/context.S
+PSCI_LIB_SOURCES	+=	lib/el3_runtime/aarch64/context.S	\
+				lib/cpus/aarch64/runtime_errata.S
 endif
 
 ifeq (${USE_COHERENT_MEM}, 1)

lib/psci/psci_private.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -304,6 +304,9 @@ int psci_spd_migrate_info(u_register_t *mpidr);
  */
 void prepare_cpu_pwr_dwn(unsigned int power_level);
 
+/* This function applies various CPU errata during power down. */
+void apply_cpu_pwr_dwn_errata(void);
+
 /* Private exported functions from psci_on.c */
 int psci_cpu_on_start(u_register_t target_cpu,
 		      const entry_point_info_t *ep);