From 1132f0688515efc017d7fcf702a164ddf1ed46a6 Mon Sep 17 00:00:00 2001 From: Nishant Sharma Date: Fri, 25 Mar 2022 23:03:31 +0000 Subject: [PATCH 01/10] refactor(spm-mm): reorganize secure partition manager shim code In preparation for adding the support for SEL0 SP in EL3 SPMC, restructure the existing SPM_MM shim code in a way that allows reuse of the code for both SPM_MM interface and FF-A EL3 SPMC interface. The code for changing exception levels is identical for both. With this restructuring of the code, the shim exception code is moved to the common sub-directory. Signed-off-by: Sayanta Pattanayak Signed-off-by: Nishant Sharma Change-Id: Iadda9cf73f12b56e6a1d31fc21b5ba5dc355867f --- .../aarch64/spm_shim_exceptions.S} | 0 .../include/spm_shim_private.h} | 8 ++++---- services/std_svc/spm/common/spm.mk | 7 ++++--- services/std_svc/spm/spm_mm/spm_mm.mk | 1 - services/std_svc/spm/spm_mm/spm_mm_setup.c | 4 ++-- services/std_svc/spm/spm_mm/spm_mm_xlat.c | 4 ++-- 6 files changed, 12 insertions(+), 12 deletions(-) rename services/std_svc/spm/{spm_mm/aarch64/spm_mm_shim_exceptions.S => common/aarch64/spm_shim_exceptions.S} (100%) rename services/std_svc/spm/{spm_mm/spm_mm_shim_private.h => common/include/spm_shim_private.h} (76%) diff --git a/services/std_svc/spm/spm_mm/aarch64/spm_mm_shim_exceptions.S b/services/std_svc/spm/common/aarch64/spm_shim_exceptions.S similarity index 100% rename from services/std_svc/spm/spm_mm/aarch64/spm_mm_shim_exceptions.S rename to services/std_svc/spm/common/aarch64/spm_shim_exceptions.S diff --git a/services/std_svc/spm/spm_mm/spm_mm_shim_private.h b/services/std_svc/spm/common/include/spm_shim_private.h similarity index 76% rename from services/std_svc/spm/spm_mm/spm_mm_shim_private.h rename to services/std_svc/spm/common/include/spm_shim_private.h index f69c748ad..bcb11476e 100644 --- a/services/std_svc/spm/spm_mm/spm_mm_shim_private.h +++ b/services/std_svc/spm/common/include/spm_shim_private.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef SPM_MM_SHIM_PRIVATE_H -#define SPM_MM_SHIM_PRIVATE_H +#ifndef SPM_SHIM_PRIVATE_H +#define SPM_SHIM_PRIVATE_H #include @@ -23,4 +23,4 @@ IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_END__, SPM_SHIM_EXCEPTIONS_END); #define SPM_SHIM_EXCEPTIONS_SIZE \ (SPM_SHIM_EXCEPTIONS_END - SPM_SHIM_EXCEPTIONS_START) -#endif /* SPM_MM_SHIM_PRIVATE_H */ +#endif /* SPM_SHIM_PRIVATE_H */ diff --git a/services/std_svc/spm/common/spm.mk b/services/std_svc/spm/common/spm.mk index 9aa96be3f..94912407e 100644 --- a/services/std_svc/spm/common/spm.mk +++ b/services/std_svc/spm/common/spm.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -10,8 +10,9 @@ endif INCLUDES += -Iservices/std_svc/spm/common/include -SPM_SOURCES := $(addprefix services/std_svc/spm/common/,\ - ${ARCH}/spm_helpers.S) +SPM_SOURCES := $(addprefix services/std_svc/spm/common/, \ + ${ARCH}/spm_helpers.S \ + ${ARCH}/spm_shim_exceptions.S) # Let the top-level Makefile know that we intend to include a BL32 image NEED_BL32 := yes diff --git a/services/std_svc/spm/spm_mm/spm_mm.mk b/services/std_svc/spm/spm_mm/spm_mm.mk index 513e8ef96..cbc794020 100644 --- a/services/std_svc/spm/spm_mm/spm_mm.mk +++ b/services/std_svc/spm/spm_mm/spm_mm.mk @@ -21,7 +21,6 @@ ifeq (${CTX_INCLUDE_FPREGS},0) endif SPM_MM_SOURCES := $(addprefix services/std_svc/spm/spm_mm/, \ - ${ARCH}/spm_mm_shim_exceptions.S \ spm_mm_main.c \ spm_mm_setup.c \ spm_mm_xlat.c) diff --git a/services/std_svc/spm/spm_mm/spm_mm_setup.c b/services/std_svc/spm/spm_mm/spm_mm_setup.c index 04dc21291..4e65c9cb1 100644 --- a/services/std_svc/spm/spm_mm/spm_mm_setup.c +++ b/services/std_svc/spm/spm_mm/spm_mm_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2021, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -21,7 +21,7 @@ #include "spm_common.h" #include "spm_mm_private.h" -#include "spm_mm_shim_private.h" +#include "spm_shim_private.h" /* Setup context of the Secure Partition */ void spm_sp_setup(sp_context_t *sp_ctx) diff --git a/services/std_svc/spm/spm_mm/spm_mm_xlat.c b/services/std_svc/spm/spm_mm/spm_mm_xlat.c index b1ca55ae3..858ca1b00 100644 --- a/services/std_svc/spm/spm_mm/spm_mm_xlat.c +++ b/services/std_svc/spm/spm_mm/spm_mm_xlat.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,7 +15,7 @@ #include #include "spm_mm_private.h" -#include "spm_mm_shim_private.h" +#include "spm_shim_private.h" /* Place translation tables by default along with the ones used by BL31. */ #ifndef PLAT_SP_IMAGE_XLAT_SECTION_NAME From 801cd3c84a7bb8a66c5a40de25e611ec6448239c Mon Sep 17 00:00:00 2001 From: Nishant Sharma Date: Tue, 27 Jun 2023 00:36:01 +0100 Subject: [PATCH 02/10] feat(el3-spmc): add a flag to enable support to load SEL0 SP Introduce a build flag for enabling the support for loading SEL0 SP in EL3 SPMC. Signed-off-by: Nishant Sharma Change-Id: I1d63ae4d0d8374a732113565be90d58861506e39 --- Makefile | 8 ++++++++ docs/components/secure-partition-manager.rst | 18 ++++++++++++++++++ docs/getting_started/build-options.rst | 4 ++++ make_helpers/defaults.mk | 3 +++ 4 files changed, 33 insertions(+) diff --git a/Makefile b/Makefile index 94dfc3e16..907ae21d4 100644 --- a/Makefile +++ b/Makefile @@ -599,6 +599,12 @@ ifneq (${SPD},none) ifneq ($(SP_LAYOUT_FILE),) BL2_ENABLE_SP_LOAD := 1 endif + + ifeq ($(SPMC_AT_EL3_SEL0_SP),1) + ifneq ($(SPMC_AT_EL3),1) + $(error SEL0 SP cannot be enabled without SPMC at EL3) + endif + endif else # All other SPDs in spd directory SPD_DIR := spd @@ -1191,6 +1197,7 @@ $(eval $(call assert_booleans,\ SPIN_ON_BL1_EXIT \ SPM_MM \ SPMC_AT_EL3 \ + SPMC_AT_EL3_SEL0_SP \ SPMD_SPM_AT_SEL2 \ ENABLE_SPMD_LP \ TRANSFER_LIST \ @@ -1355,6 +1362,7 @@ $(eval $(call add_defines,\ SPIN_ON_BL1_EXIT \ SPM_MM \ SPMC_AT_EL3 \ + SPMC_AT_EL3_SEL0_SP \ SPMD_SPM_AT_SEL2 \ TRANSFER_LIST \ TRUSTED_BOARD_BOOT \ diff --git a/docs/components/secure-partition-manager.rst b/docs/components/secure-partition-manager.rst index d4f0b0081..5d3adec82 100644 --- a/docs/components/secure-partition-manager.rst +++ b/docs/components/secure-partition-manager.rst @@ -152,6 +152,8 @@ SPMC located at S-EL1, S-EL2 or EL3: exception level is set to S-EL1. ``SPMD_SPM_AT_SEL2`` is enabled. The context save/restore routine and exhaustive list of registers is visible at `[4]`_. +- **SPMC_AT_EL3_SEL0_SP**: this option enables the support to load SEL0 SP + when SPMC at EL3 support is enabled. - **SP_LAYOUT_FILE**: this option specifies a text description file providing paths to SP binary images and manifests in DTS format (see `Describing secure partitions`_). It @@ -257,6 +259,22 @@ Sample TF-A build command line when the SPMC is located at EL3: PLAT=fvp \ all fip +Sample TF-A build command line when the SPMC is located at EL3 and SEL0 SP is +enabled: + +.. code:: shell + + make \ + CROSS_COMPILE=aarch64-none-elf- \ + SPD=spmd \ + SPMD_SPM_AT_SEL2=0 \ + SPMC_AT_EL3=1 \ + SPMC_AT_EL3_SEL0_SP=1 \ + BL32= \ + BL33= \ + PLAT=fvp \ + all fip + FVP model invocation ==================== diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index c045a6aa2..cf8002d64 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -900,6 +900,10 @@ Common build options disabled). This configuration supports pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` extension). This is an experimental feature. +- ``SPMC_AT_EL3_SEL0_SP`` : Boolean option to enable SEL0 SP load support when + ``SPMC_AT_EL3`` is enabled. The default value if ``0`` (disabled). This + option cannot be enabled (``1``) when (``SPMC_AT_EL3``) is disabled. + - ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index f31365a1f..ea22655ce 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -240,6 +240,9 @@ SPM_MM := 0 # Use the FF-A SPMC implementation in EL3. SPMC_AT_EL3 := 0 +# Enable SEL0 SP when SPMC is enabled at EL3 +SPMC_AT_EL3_SEL0_SP :=0 + # Use SPM at S-EL2 as a default config for SPMD SPMD_SPM_AT_SEL2 := 1 From 5df1dccd0be06cc45e82a57dc01be5b6b5d1a21b Mon Sep 17 00:00:00 2001 From: Nishant Sharma Date: Thu, 12 Oct 2023 10:37:54 +0100 Subject: [PATCH 03/10] feat(arm): reuse SPM_MM specific defines for SPMC_AT_EL3 For EL3 SPMC configuration enabled platforms, allow the reuse of SPM_MM specific definitions. Signed-off-by: Sayanta Pattanayak Signed-off-by: Nishant Sharma Change-Id: Ia24b97343c7b8c6b22a4d54c5bb9cee2c480241f --- include/plat/arm/common/plat_arm.h | 2 +- plat/arm/css/sgi/include/sgi_base_platform_def.h | 8 ++++---- plat/arm/css/sgi/sgi_plat_v2.c | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index 2fdbfb7d0..f71480f75 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h @@ -53,7 +53,7 @@ typedef struct arm_tzc_regions_info { PLAT_ARM_TZC_NS_DEV_ACCESS} #endif -#if SPM_MM +#if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) #define ARM_TZC_REGIONS_DEF \ {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ TZC_REGION_S_RDWR, 0}, \ diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h index b9c785f81..8a13bf33e 100644 --- a/plat/arm/css/sgi/include/sgi_base_platform_def.h +++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -33,7 +33,7 @@ * chips are accessed - secure ram, css device and soc device regions. */ #if defined(IMAGE_BL31) -# if SPM_MM +# if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) # define PLAT_ARM_MMAP_ENTRIES (9 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) # define MAX_XLAT_TABLES (7 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) # define PLAT_SP_IMAGE_MMAP_REGIONS 10 @@ -210,7 +210,7 @@ #define PLAT_SP_PRI 0x10 #endif -#if SPM_MM && RAS_FFH_SUPPORT +#if (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)) && RAS_FFH_SUPPORT /* * CPER buffer memory of 128KB is reserved and it is placed adjacent to the * memory shared between EL3 and S-EL0. @@ -232,7 +232,7 @@ #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ PLAT_SP_IMAGE_NS_BUF_SIZE + \ CSS_SGI_SP_CPER_BUF_SIZE) -#elif SPM_MM +#elif (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)) /* * Secure partition stack follows right after the memory region that is shared * between EL3 and S-EL0. diff --git a/plat/arm/css/sgi/sgi_plat_v2.c b/plat/arm/css/sgi/sgi_plat_v2.c index 8de0efe30..85f99d44d 100644 --- a/plat/arm/css/sgi/sgi_plat_v2.c +++ b/plat/arm/css/sgi/sgi_plat_v2.c @@ -54,7 +54,7 @@ const mmap_region_t plat_arm_mmap[] = { #if ARM_BL31_IN_DRAM ARM_MAP_BL31_SEC_DRAM, #endif -#if SPM_MM +#if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) ARM_SP_IMAGE_MMAP, #endif #if TRUSTED_BOARD_BOOT && !RESET_TO_BL2 @@ -73,7 +73,7 @@ const mmap_region_t plat_arm_mmap[] = { CSS_SGI_MAP_DEVICE, SOC_PLATFORM_PERIPH_MAP_DEVICE, SOC_SYSTEM_PERIPH_MAP_DEVICE, -#if SPM_MM +#if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) ARM_SPM_BUF_EL3_MMAP, #endif {0} From f5e1bed2669cce46a1d7c6b8d3f8f884b4d589b3 Mon Sep 17 00:00:00 2001 From: Nishant Sharma Date: Thu, 12 Oct 2023 10:43:16 +0100 Subject: [PATCH 04/10] feat(bl31): reuse SPM_MM specific defines for SPMC_AT_EL3 For EL3 SPMC configuration enabled platforms, allow the reuse of SPM_MM specific definitions. Signed-off-by: Nishant Sharma Change-Id: I5ef694f7e2f6d48ec7db26f92ccb350ed537e3f1 --- bl31/bl31.ld.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index 7a8c41ab2..773b41d3e 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -101,7 +101,7 @@ SECTIONS { ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, "cpu_ops not defined for this platform.") -#if SPM_MM +#if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) # ifndef SPM_SHIM_EXCEPTIONS_VMA # define SPM_SHIM_EXCEPTIONS_VMA RAM # endif /* SPM_SHIM_EXCEPTIONS_VMA */ @@ -128,7 +128,7 @@ SECTIONS { PROVIDE(__SPM_SHIM_EXCEPTIONS_LMA__ = LOADADDR(.spm_shim_exceptions)); . = LOADADDR(.spm_shim_exceptions) + SIZEOF(.spm_shim_exceptions); -#endif /* SPM_MM */ +#endif /* SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) */ __RW_START__ = .; From 6e92a82c81d2b0e49df730f68c8312beec1d3b48 Mon Sep 17 00:00:00 2001 From: Nishant Sharma Date: Thu, 12 Oct 2023 10:45:28 +0100 Subject: [PATCH 05/10] feat(ras): reuse SPM_MM specific defines for SPMC_AT_EL3 For EL3 SPMC configuration enabled platforms, allow the reuse of SPM_MM specific definitions. Signed-off-by: Nishant Sharma Change-Id: Ic88db49d4f854c718d064b2c301a639fc2df2857 --- plat/common/aarch64/plat_ehf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/plat/common/aarch64/plat_ehf.c b/plat/common/aarch64/plat_ehf.c index be0fac170..41b175d56 100644 --- a/plat/common/aarch64/plat_ehf.c +++ b/plat/common/aarch64/plat_ehf.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2020, Broadcom * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,7 +25,7 @@ ehf_pri_desc_t plat_exceptions[] = { EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_NORMAL_PRI), #endif -#if SPM_MM +#if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) #if RAS_FFH_SUPPORT #if (PLAT_SP_PRI != PLAT_RAS_PRI) EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SP_PRI), From b4bed4b769e907c8431b07f698da24660dfe0059 Mon Sep 17 00:00:00 2001 From: Nishant Sharma Date: Wed, 4 Oct 2023 07:27:15 +0100 Subject: [PATCH 06/10] feat(rdn2): add defines needed for spmc-el3 Add the following platform specific flags to enable SPMC build. SECURE_PARTITION_COUNT: Number of secure partitions supported NS_PARTITION_COUNT: Number of non secure partitions supported MAX_EL3_LP_DESCS_COUNT: Number of logical partitions supported Signed-off-by: Sayanta Pattanayak Signed-off-by: Nishant Sharma Change-Id: I33d46be9dffd0acfc088bc1701dc0b1ed92dbf46 --- plat/arm/board/rdn2/include/platform_def.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/plat/arm/board/rdn2/include/platform_def.h b/plat/arm/board/rdn2/include/platform_def.h index ff1a4377f..2391b7254 100644 --- a/plat/arm/board/rdn2/include/platform_def.h +++ b/plat/arm/board/rdn2/include/platform_def.h @@ -102,4 +102,25 @@ #define PLAT_REBOOT_PRI GIC_HIGHEST_SEC_PRIORITY #define PLAT_EHF_DESC EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_REBOOT_PRI) +/* + * Number of Secure Partitions supported. + * SPMC at EL3, uses this count to configure the maximum number of supported + * secure partitions. + */ +#define SECURE_PARTITION_COUNT 1 + +/* + * Number of NWd Partitions supported. + * SPMC at EL3, uses this count to configure the maximum number of supported + * nwld partitions. + */ +#define NS_PARTITION_COUNT 1 + +/* + * Number of Logical Partitions supported. + * SPMC at EL3, uses this count to configure the maximum number of supported + * logical partitions. + */ +#define MAX_EL3_LP_DESCS_COUNT 1 + #endif /* PLATFORM_DEF_H */ From 549bc04f148f3b42ea0808b9ab0794a48d67007d Mon Sep 17 00:00:00 2001 From: Nishant Sharma Date: Thu, 28 Apr 2022 00:13:50 +0100 Subject: [PATCH 07/10] feat(spm): separate StMM SP specifics to add support for a S-EL0 SP This patch separates the code from SPM_MM to get xlat table context and move it to a common location. In addition, only APIs required from both SPM_MM and FF-A EL3 SPMC are moved to the common location. This allows understanding better what is required to support a S-EL0 SP instead of trying to retrofit what already exists. Signed-off-by: Achin Gupta Signed-off-by: Nishant Sharma Change-Id: I142d7fbef5239869176d0de93842c66051d7ed78 --- .../std_svc/spm/common/include/spm_common.h | 6 +++- services/std_svc/spm/common/spm.mk | 5 ++++ services/std_svc/spm/common/spm_xlat_common.c | 30 +++++++++++++++++++ services/std_svc/spm/spm_mm/spm_mm_private.h | 4 +-- services/std_svc/spm/spm_mm/spm_mm_xlat.c | 22 -------------- 5 files changed, 41 insertions(+), 26 deletions(-) create mode 100644 services/std_svc/spm/common/spm_xlat_common.c diff --git a/services/std_svc/spm/common/include/spm_common.h b/services/std_svc/spm/common/include/spm_common.h index 68805fc4d..c73691953 100644 --- a/services/std_svc/spm/common/include/spm_common.h +++ b/services/std_svc/spm/common/include/spm_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -32,11 +32,15 @@ #ifndef __ASSEMBLER__ #include +#include /* Assembly helpers */ uint64_t spm_secure_partition_enter(uint64_t *c_rt_ctx); void __dead2 spm_secure_partition_exit(uint64_t c_rt_ctx, uint64_t ret); +/* Helper to obtain a reference to the SP's translation table context */ +xlat_ctx_t *spm_get_sp_xlat_context(void); + #endif /* __ASSEMBLER__ */ #endif /* SPM_COMMON_H */ diff --git a/services/std_svc/spm/common/spm.mk b/services/std_svc/spm/common/spm.mk index 94912407e..65fd72aa4 100644 --- a/services/std_svc/spm/common/spm.mk +++ b/services/std_svc/spm/common/spm.mk @@ -14,5 +14,10 @@ SPM_SOURCES := $(addprefix services/std_svc/spm/common/, \ ${ARCH}/spm_helpers.S \ ${ARCH}/spm_shim_exceptions.S) +ifeq (1, $(filter 1, ${SPM_MM} ${SPMC_AT_EL3_SEL0_SP})) +SPM_SOURCES += $(addprefix services/std_svc/spm/common/, \ + spm_xlat_common.c) +endif + # Let the top-level Makefile know that we intend to include a BL32 image NEED_BL32 := yes diff --git a/services/std_svc/spm/common/spm_xlat_common.c b/services/std_svc/spm/common/spm_xlat_common.c new file mode 100644 index 000000000..a463c8b49 --- /dev/null +++ b/services/std_svc/spm/common/spm_xlat_common.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +/* Place translation tables by default along with the ones used by BL31. */ +#ifndef PLAT_SP_IMAGE_XLAT_SECTION_NAME +#define PLAT_SP_IMAGE_XLAT_SECTION_NAME ".xlat_table" +#endif +#ifndef PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME +#define PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME ".bss" +#endif + +/* Allocate and initialise the translation context for the secure partitions. */ +REGISTER_XLAT_CONTEXT2(sp, + PLAT_SP_IMAGE_MMAP_REGIONS, + PLAT_SP_IMAGE_MAX_XLAT_TABLES, + PLAT_VIRT_ADDR_SPACE_SIZE, PLAT_PHY_ADDR_SPACE_SIZE, + EL1_EL0_REGIME, PLAT_SP_IMAGE_XLAT_SECTION_NAME, + PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME); + +/* Get handle of Secure Partition translation context */ +xlat_ctx_t *spm_get_sp_xlat_context(void) +{ + return &sp_xlat_ctx; +}; diff --git a/services/std_svc/spm/spm_mm/spm_mm_private.h b/services/std_svc/spm/spm_mm/spm_mm_private.h index 0eff1c071..3a52a3ee8 100644 --- a/services/std_svc/spm/spm_mm/spm_mm_private.h +++ b/services/std_svc/spm/spm_mm/spm_mm_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -55,8 +55,6 @@ typedef struct sp_context { void spm_sp_setup(sp_context_t *sp_ctx); -xlat_ctx_t *spm_get_sp_xlat_context(void); - int32_t spm_memory_attributes_get_smc_handler(sp_context_t *sp_ctx, uintptr_t base_va); int spm_memory_attributes_set_smc_handler(sp_context_t *sp_ctx, diff --git a/services/std_svc/spm/spm_mm/spm_mm_xlat.c b/services/std_svc/spm/spm_mm/spm_mm_xlat.c index 858ca1b00..01d95c77c 100644 --- a/services/std_svc/spm/spm_mm/spm_mm_xlat.c +++ b/services/std_svc/spm/spm_mm/spm_mm_xlat.c @@ -17,31 +17,9 @@ #include "spm_mm_private.h" #include "spm_shim_private.h" -/* Place translation tables by default along with the ones used by BL31. */ -#ifndef PLAT_SP_IMAGE_XLAT_SECTION_NAME -#define PLAT_SP_IMAGE_XLAT_SECTION_NAME ".xlat_table" -#endif -#ifndef PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME -#define PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME ".bss" -#endif - -/* Allocate and initialise the translation context for the secure partitions. */ -REGISTER_XLAT_CONTEXT2(sp, - PLAT_SP_IMAGE_MMAP_REGIONS, - PLAT_SP_IMAGE_MAX_XLAT_TABLES, - PLAT_VIRT_ADDR_SPACE_SIZE, PLAT_PHY_ADDR_SPACE_SIZE, - EL1_EL0_REGIME, PLAT_SP_IMAGE_XLAT_SECTION_NAME, - PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME); - /* Lock used for SP_MEMORY_ATTRIBUTES_GET and SP_MEMORY_ATTRIBUTES_SET */ static spinlock_t mem_attr_smc_lock; -/* Get handle of Secure Partition translation context */ -xlat_ctx_t *spm_get_sp_xlat_context(void) -{ - return &sp_xlat_ctx; -}; - /* * Attributes are encoded using a different format in the SMC interface than in * the Trusted Firmware, where the mmap_attr_t enum type is used. This function From f45893426546703d9e21970889e6333ca30c0dd7 Mon Sep 17 00:00:00 2001 From: Nishant Sharma Date: Sat, 26 Mar 2022 00:34:05 +0000 Subject: [PATCH 08/10] feat(rdn2): introduce accessor function to obtain datastore In order to provide the EL3 SPMC a sufficient datastore to record memory descriptor, introduce an accessor function so that the backing memory can be allocated in a platform defined manner to accommodate memory constraints and desired usecases. Signed-off-by: Nishant Sharma Change-Id: If5842e79c2ad22ccc17362b114f47d9900d82f7e --- plat/arm/board/rdn2/rdn2_plat.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/plat/arm/board/rdn2/rdn2_plat.c b/plat/arm/board/rdn2/rdn2_plat.c index e8a967e00..f044558d8 100644 --- a/plat/arm/board/rdn2/rdn2_plat.c +++ b/plat/arm/board/rdn2/rdn2_plat.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -141,3 +141,17 @@ void bl31_platform_setup(void) #endif } #endif /* IMAGE_BL31 */ + +#if SPMC_AT_EL3 + +#define DATASTORE_SIZE 1024 + +__section("arm_el3_tzc_dram") uint8_t plat_spmc_shmem_datastore[DATASTORE_SIZE]; + +int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size) +{ + *datastore = plat_spmc_shmem_datastore; + *size = DATASTORE_SIZE; + return 0; +} +#endif From f99dcbace7015169ac5d230b8007686d144962fb Mon Sep 17 00:00:00 2001 From: Nishant Sharma Date: Wed, 13 Jul 2022 10:19:58 +0100 Subject: [PATCH 09/10] feat(rdn2): add plat hook for memory transaction RdN2 does not make MEM_SHARE/LEND requests. Instead, add a dummy implementation of memory management related platform hooks. Signed-off-by: Nishant Sharma Change-Id: Ifce55b6661f03d379e2fd2dc5625200d550d8038 --- plat/arm/board/rdn2/rdn2_plat.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/plat/arm/board/rdn2/rdn2_plat.c b/plat/arm/board/rdn2/rdn2_plat.c index f044558d8..fc016aef0 100644 --- a/plat/arm/board/rdn2/rdn2_plat.c +++ b/plat/arm/board/rdn2/rdn2_plat.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -154,4 +155,18 @@ int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size) *size = DATASTORE_SIZE; return 0; } + +/* + * Add dummy implementations of memory management related platform hooks. + * Memory share/lend operation are not required on RdN2 platform. + */ +int plat_spmc_shmem_begin(struct ffa_mtd *desc) +{ + return 0; +} + +int plat_spmc_shmem_reclaim(struct ffa_mtd *desc) +{ + return 0; +} #endif From c47d0491ed078cfa8ca400e182fd4a44acd8041a Mon Sep 17 00:00:00 2001 From: Nishant Sharma Date: Wed, 28 Jun 2023 11:46:00 +0100 Subject: [PATCH 10/10] feat(rdn2): introduce platform handler for Group0 interrupt This patch introduces a handler for RDN2 platform to triage Group0 secure interrupts. Currently, it is empty but serves as a placeholder for future Group0 interrupt sources. Signed-off-by: Nishant Sharma Change-Id: If0b64e507e9105813d9a5d16f70101cf0d8ca5a4 --- plat/arm/board/rdn2/rdn2_plat.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/plat/arm/board/rdn2/rdn2_plat.c b/plat/arm/board/rdn2/rdn2_plat.c index fc016aef0..f1174562c 100644 --- a/plat/arm/board/rdn2/rdn2_plat.c +++ b/plat/arm/board/rdn2/rdn2_plat.c @@ -169,4 +169,14 @@ int plat_spmc_shmem_reclaim(struct ffa_mtd *desc) { return 0; } + +int plat_spmd_handle_group0_interrupt(uint32_t intid) +{ + /* + * As of now, there are no sources of Group0 secure interrupt enabled + * for RDN2. + */ + (void)intid; + return -1; +} #endif