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fix(zynqmp): move EM SMC range to SIP range
EM SMC where out of SIP range which is 15:0 bits only. EM was used 19:17 bits which is wrong but no code was checking it. That's why vove EM SMC to SIP range. Change-Id: I83f998a17a8b82b2c25ea8c9b247e42642c82178 Signed-off-by: Michal Simek <michal.simek@amd.com>
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2 changed files with 9 additions and 8 deletions
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@ -359,7 +359,7 @@ enum pm_clock_div_id {
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* EM API IDs
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*/
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enum em_api_id {
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EM_SET_ACTION = 1,
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EM_SET_ACTION = 0x3001,
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EM_REMOVE_ACTION,
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EM_SEND_ERRORS,
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};
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2023, Advanced Micro Devices Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -29,7 +30,7 @@
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#define XLNX_FID_MASK GENMASK(23, 12)
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#define PM_FID_VALUE 0u
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#define IPI_FID_VALUE 0x1000u
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#define EM_FID_VALUE 0xE0000u
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#define EM_FID_VALUE 0x3000u
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#define is_em_fid(_fid) (((_fid) & XLNX_FID_MASK) == EM_FID_VALUE)
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#define is_pm_fid(_fid) (((_fid) & XLNX_FID_MASK) == PM_FID_VALUE)
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#define is_ipi_fid(_fid) (((_fid) & XLNX_FID_MASK) == IPI_FID_VALUE)
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@ -68,17 +69,17 @@ static uintptr_t sip_svc_smc_handler(uint32_t smc_fid,
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VERBOSE("SMCID: 0x%08x, x1: 0x%016" PRIx64 ", x2: 0x%016" PRIx64 ", x3: 0x%016" PRIx64 ", x4: 0x%016" PRIx64 "\n",
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smc_fid, x1, x2, x3, x4);
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/* Let EM SMC handler deal with EM-related requests */
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if (is_em_fid(smc_fid)) {
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return em_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle,
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flags);
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}
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if (smc_fid & SIP_FID_MASK) {
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WARN("SMC out of SiP assinged range: 0x%x\n", smc_fid);
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SMC_RET1(handle, SMC_UNK);
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}
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/* Let EM SMC handler deal with EM-related requests */
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if (is_em_fid(smc_fid)) {
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return em_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle,
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flags);
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}
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/* Let PM SMC handler deal with PM-related requests */
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if (is_pm_fid(smc_fid)) {
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return pm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle,
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