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feat(qemu-sbsa): add support for RME on SBSA machine
Add the necessary foundation to support Arm's RME extension on the SBSA reference architecture. Change-Id: If5a63ed0015cb33fcae367ff2cded811bbdc1e54 Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
This commit is contained in:
Mathieu Poirier
parent
fb4edc35bc
commit
acb09373ba
3 changed files with 181 additions and 4 deletions
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@ -129,7 +129,8 @@
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#define BL1_RO_BASE SEC_ROM_BASE
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#define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE)
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#define BL1_RW_BASE (BL1_RW_LIMIT - BL1_SIZE)
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#define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE)
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#define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE - \
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RME_GPT_DRAM_SIZE)
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/*
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* BL2 specific defines.
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@ -147,7 +148,7 @@
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* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
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* current BL3-1 debug size plus a little space for growth.
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*/
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#define BL31_SIZE 0x300000
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#define BL31_SIZE 0x400000
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#define BL31_BASE (BL31_LIMIT - BL31_SIZE)
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#define BL31_LIMIT (BL1_RW_BASE)
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#define BL31_PROGBITS_LIMIT BL1_RW_BASE
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@ -162,8 +163,8 @@
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#define BL32_SRAM_LIMIT BL2_BASE
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#define BL32_MEM_BASE BL_RAM_BASE
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#define BL32_MEM_SIZE (BL_RAM_SIZE - BL1_SIZE - \
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BL2_SIZE - BL31_SIZE)
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#define BL32_MEM_SIZE (BL_RAM_SIZE - RME_GPT_DRAM_SIZE - \
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BL1_SIZE - BL2_SIZE - BL31_SIZE)
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#define BL32_BASE BL32_SRAM_BASE
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#define BL32_LIMIT BL32_SRAM_LIMIT
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@ -175,6 +176,9 @@
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#if SPM_MM
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#define MAX_MMAP_REGIONS 12
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#define MAX_XLAT_TABLES 12
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#elif ENABLE_RME
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#define MAX_MMAP_REGIONS 14
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#define MAX_XLAT_TABLES 14
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#else
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#define MAX_MMAP_REGIONS 11
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#define MAX_XLAT_TABLES 11
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@ -385,6 +389,105 @@
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#define QEMU_PRI_BITS 2
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#define PLAT_SP_PRI 0x20
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#if !ENABLE_RME
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#define RME_GPT_DRAM_SIZE 0
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#define NS_DRAM0_BASE_OFFSET 0
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#else /* !ENABLE_RME */
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/*
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* SBSA RAM starts at 1TB and we support up to 1TB of RAM. As such we
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* have 2TB of physical address space to cover. Since the GPT size can be
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* 4GB, 64GB, 1TB, 4TB and so on, we need to select 4GB. Note that it is
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* possible to support more than 1TB of RAM but that will take more room in
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* secure memory due to the L1 GPTES. See PLAT_QEMU_L1_GPT_SIZE for details.
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*
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* 4TB / 1GB == 4096 GPTEs
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* 4096 * 8 (bytes per GPTE) == 32768 i.e 8 pages
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*/
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#define PLAT_QEMU_L0_GPT_SIZE (8 * PAGE_SIZE)
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#define PLAT_QEMU_L0_GPT_BASE (PLAT_QEMU_L1_GPT_BASE - \
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(PLAT_QEMU_L0_GPT_SIZE + \
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PLAT_QEMU_GPT_BITLOCK_SIZE + \
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PLAT_QEMU_GPT_ALIGNMENT))
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#if RME_GPT_BITLOCK_BLOCK
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/*
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* 4TB / (RME_GPT_BITLOCK_BLOCK * 512M * 8) == 1024
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*/
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#define PLAT_QEMU_GPT_BITLOCK_SIZE (1 * PAGE_SIZE)
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/*
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* PLAT_QEMU_L0_GPT_SIZE is 8 pages and PLAT_QEMU_GPT_BITLOCK_SIZE
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* is 1 page. As such we need 7 pages to have an 8 page alignment.
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*/
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#define PLAT_QEMU_GPT_ALIGNMENT (7 * PAGE_SIZE)
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#else /* RME_GPT_BITLOCK_BLOCK */
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#define PLAT_QEMU_GPT_BITLOCK_SIZE 0
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#define PLAT_QEMU_GPT_ALIGNMENT 0
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#endif /* RME_GPT_BITLOCK_BLOCK */
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/*
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* If we have 1TB of RAM and each L1GPT covers 1GB, we need 1024 L1GPTs. With
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* one more L1GPT to cover the other physical address spaces (see pas_regions[]
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* in qemu_bl31_setup.c), we need a total of 1025 L1GPTs. Each L1GPT is 131072
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* bytes, so we need 1025 * 131072 bytes = 0x8020000 of RAM to hold the L1GPTS.
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*/
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#define PLAT_QEMU_L1_GPT_SIZE UL(0x08020000)
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#define PLAT_QEMU_L1_GPT_BASE (BL_RAM_BASE + BL_RAM_SIZE - \
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PLAT_QEMU_L1_GPT_SIZE)
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#define PLAT_QEMU_L1_GPT_END (PLAT_QEMU_L1_GPT_BASE + \
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PLAT_QEMU_L1_GPT_SIZE - 1U)
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#define RME_GPT_DRAM_BASE PLAT_QEMU_L0_GPT_BASE
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#define RME_GPT_DRAM_SIZE (PLAT_QEMU_L1_GPT_SIZE + \
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PLAT_QEMU_L0_GPT_SIZE + \
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PLAT_QEMU_GPT_BITLOCK_SIZE + \
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PLAT_QEMU_GPT_ALIGNMENT)
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#ifndef __ASSEMBLER__
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/* L0 table greater than 4KB must be naturally aligned */
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CASSERT((PLAT_QEMU_L0_GPT_BASE & (PLAT_QEMU_L0_GPT_SIZE - 1)) == 0,
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assert_l0_gpt_naturally_aligned);
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#endif
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/* Reserved some DRAM space for RMM (1072MB) */
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#define REALM_DRAM_BASE PLAT_QEMU_DRAM0_BASE
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#define REALM_DRAM_SIZE 0x43000000
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#define PLAT_QEMU_RMM_SIZE (REALM_DRAM_SIZE - RMM_SHARED_SIZE)
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#define PLAT_QEMU_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */
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#define RMM_BASE (REALM_DRAM_BASE)
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#define RMM_LIMIT (RMM_BASE + PLAT_QEMU_RMM_SIZE)
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#define RMM_SHARED_BASE (RMM_LIMIT)
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#define RMM_SHARED_SIZE PLAT_QEMU_RMM_SHARED_SIZE
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#define MAP_GPT_L0_REGION MAP_REGION_FLAT( \
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PLAT_QEMU_L0_GPT_BASE, \
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(PLAT_QEMU_L0_GPT_SIZE + \
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PLAT_QEMU_GPT_BITLOCK_SIZE + \
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PLAT_QEMU_GPT_ALIGNMENT), \
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MT_MEMORY | MT_RW | EL3_PAS)
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#define MAP_GPT_L1_REGION MAP_REGION_FLAT( \
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PLAT_QEMU_L1_GPT_BASE, \
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PLAT_QEMU_L1_GPT_SIZE, \
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MT_MEMORY | MT_RW | EL3_PAS)
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/*
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* We add the RMM_SHARED size to RMM mapping to map the region as a block.
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* Else we end up requiring more pagetables in BL2 for ROMLIB build.
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*/
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#define MAP_RMM_DRAM MAP_REGION_FLAT( \
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RMM_BASE, \
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(PLAT_QEMU_RMM_SIZE + \
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RMM_SHARED_SIZE), \
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MT_MEMORY | MT_RW | MT_REALM)
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#define MAP_RMM_SHARED_MEM MAP_REGION_FLAT( \
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RMM_SHARED_BASE, \
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RMM_SHARED_SIZE, \
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MT_MEMORY | MT_RW | MT_REALM)
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/* When RME is enabled, the base of NS DRAM is moved forward after the RMM */
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#define NS_DRAM0_BASE_OFFSET REALM_DRAM_SIZE
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#endif /* !ENABLE_RME */
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#endif /* PLATFORM_DEF_H */
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66
plat/qemu/qemu_sbsa/include/qemu_sbsa_pas_def.h
Normal file
66
plat/qemu/qemu_sbsa/include/qemu_sbsa_pas_def.h
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@ -0,0 +1,66 @@
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/*
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* Copyright (c) 2024-2025, Linaro Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef QEMU_PAS_DEF_H
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#define QEMU_PAS_DEF_H
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#include <lib/gpt_rme/gpt_rme.h>
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#include "platform_def.h"
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/*****************************************************************************
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* PAS regions used to initialize the Granule Protection Table (GPT)
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****************************************************************************/
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/* EL3 SRAM */
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#define QEMU_PAS_ROOT_BASE (BL32_MEM_BASE + BL32_MEM_SIZE)
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#define QEMU_PAS_ROOT_SIZE (BL_RAM_SIZE - \
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(BL32_MEM_SIZE + RME_GPT_DRAM_SIZE))
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/* Secure DRAM */
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#define QEMU_PAS_SEC_BASE BL32_MEM_BASE /* BL32_SRAM_BASE */
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#define QEMU_PAS_SEC_SIZE BL32_MEM_SIZE
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/* GPTs */
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#define QEMU_PAS_GPT_BASE RME_GPT_DRAM_BASE /* PLAT_QEMU_L0_GPT_BASE */
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#define QEMU_PAS_GPT_SIZE RME_GPT_DRAM_SIZE
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/* RMM */
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#define QEMU_PAS_RMM_BASE RMM_BASE
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#define QEMU_PAS_RMM_SIZE PLAT_QEMU_RMM_SIZE
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/* Shared area between EL3 and RMM */
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#define QEMU_PAS_RMM_SHARED_BASE RMM_SHARED_BASE
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#define QEMU_PAS_RMM_SHARED_SIZE RMM_SHARED_SIZE
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#define QEMU_PAS_ROOT GPT_MAP_REGION_GRANULE(QEMU_PAS_ROOT_BASE, \
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QEMU_PAS_ROOT_SIZE, \
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GPT_GPI_ROOT)
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#define QEMU_PAS_SECURE GPT_MAP_REGION_GRANULE(QEMU_PAS_SEC_BASE, \
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QEMU_PAS_SEC_SIZE, \
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GPT_GPI_SECURE)
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#define QEMU_PAS_GPTS GPT_MAP_REGION_GRANULE(QEMU_PAS_GPT_BASE, \
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QEMU_PAS_GPT_SIZE, \
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GPT_GPI_ROOT)
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/*
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* NS0 base address and size are fetched from the DT at runtime.
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* See bl31_adjust_pas_regions() for details
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*/
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#define QEMU_PAS_NS0 GPT_MAP_REGION_GRANULE(0, 0, GPT_GPI_NS)
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#define QEMU_PAS_REALM GPT_MAP_REGION_GRANULE(QEMU_PAS_RMM_BASE, \
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QEMU_PAS_RMM_SIZE + \
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QEMU_PAS_RMM_SHARED_SIZE, \
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GPT_GPI_REALM)
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/* Cover 4TB with L0GTP */
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#define PLATFORM_GPCCR_PPS GPCCR_PPS_4TB
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/* GPT Configuration options */
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#define PLATFORM_L0GPTSZ GPCCR_L0GPTSZ_30BITS
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#endif /* QEMU_PAS_DEF_H */
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8
plat/qemu/qemu_sbsa/trp/trp-qemu_sbsa.mk
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8
plat/qemu/qemu_sbsa/trp/trp-qemu_sbsa.mk
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@ -0,0 +1,8 @@
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#
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# Copyright (c) 2024-2025, Linaro Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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include plat/qemu/common/trp/trp-qemu-common.mk
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