diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 65621392c..117372f45 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -311,10 +311,6 @@ For Cortex-A78, the following errata build flags are defined : - ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0. -- ``ERRATA_A78_2132060``: This applies errata 2132060 workaround to Cortex-A78 - CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It - is still open. - - ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue is present in r0p0 but there is no workaround. It is still open. @@ -377,10 +373,6 @@ For Cortex-A78C, the following errata build flags are defined : Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is fixed in r0p1. -- ``ERRATA_A78C_2132064`` : This applies errata 2132064 workaround to - Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and - it is still open. - - ``ERRATA_A78C_2242638`` : This applies errata 2242638 workaround to Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and it is still open. @@ -505,10 +497,6 @@ For Neoverse V1, the following errata build flags are defined : CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. It is still open. -- ``ERRATA_V1_2108267``: This applies errata 2108267 workaround to Neoverse-V1 - CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. - It is still open. - - ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the issue is present in r0p0 as well but there is no workaround for that @@ -545,10 +533,6 @@ For Neoverse V1, the following errata build flags are defined : For Neoverse V2, the following errata build flags are defined : -- ``ERRATA_V2_2331132``: This applies errata 2331132 workaround to Neoverse-V2 - CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is still - open. - - ``ERRATA_V2_2618597``: This applies errata 2618597 workaround to Neoverse-V2 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. @@ -609,10 +593,6 @@ For Cortex-A710, the following errata build flags are defined : Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and is still open. -- ``ERRATA_A710_2058056``: This applies errata 2058056 workaround to - Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 - and r2p1 of the CPU and is still open. - - ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU and is fixed in r2p1. @@ -686,9 +666,6 @@ For Neoverse N2, the following errata build flags are defined : - ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. -- ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2 - CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is still open. - - ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. @@ -752,10 +729,6 @@ For Cortex-X2, the following errata build flags are defined : CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU, it is still open. -- ``ERRATA_X2_2058056``: This applies errata 2058056 workaround to Cortex-X2 - CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the CPU, - it is still open. - - ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2 CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open. @@ -806,10 +779,6 @@ For Cortex-X2, the following errata build flags are defined : For Cortex-X3, the following errata build flags are defined : -- ``ERRATA_X3_2070301``: This applies errata 2070301 workaround to the Cortex-X3 - CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 of - the CPU and is still open. - - ``ERRATA_X3_2266875``: This applies errata 2266875 workaround to the Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it is fixed in r1p1. diff --git a/include/lib/cpus/aarch64/cortex_a710.h b/include/lib/cpus/aarch64/cortex_a710.h index 650193cc0..a47a47ea0 100644 --- a/include/lib/cpus/aarch64/cortex_a710.h +++ b/include/lib/cpus/aarch64/cortex_a710.h @@ -51,14 +51,6 @@ #define CORTEX_A710_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) #define CORTEX_A710_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) -/******************************************************************************* - * CPU Auxiliary Control register specific definitions. - ******************************************************************************/ -#define CORTEX_A710_CPUECTLR2_EL1 S3_0_C15_C1_5 -#define CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) -#define CPUECTLR2_EL1_PF_MODE_LSB U(11) -#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) - /******************************************************************************* * CPU Selected Instruction Private register specific definitions. ******************************************************************************/ diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h index 2984f82a8..203bdfdbf 100644 --- a/include/lib/cpus/aarch64/cortex_a78.h +++ b/include/lib/cpus/aarch64/cortex_a78.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2023, Arm Limited. All rights reserved. + * Copyright (c) 2019-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,9 +19,6 @@ ******************************************************************************/ #define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4 #define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) -#define CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3) -#define CPUECTLR_EL1_PF_MODE_LSB U(6) -#define CPUECTLR_EL1_PF_MODE_WIDTH U(2) /******************************************************************************* * CPU Power Control register specific definitions diff --git a/include/lib/cpus/aarch64/cortex_a78c.h b/include/lib/cpus/aarch64/cortex_a78c.h index d600ecab5..20331203b 100644 --- a/include/lib/cpus/aarch64/cortex_a78c.h +++ b/include/lib/cpus/aarch64/cortex_a78c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * Copyright (c) 2021-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,8 +24,6 @@ * CPU Extended Control register specific definitions. ******************************************************************************/ #define CORTEX_A78C_CPUECTLR_EL1 S3_0_C15_C1_4 -#define CORTEX_A78C_CPUECTLR_EL1_BIT_6 (ULL(1) << 6) -#define CORTEX_A78C_CPUECTLR_EL1_BIT_7 (ULL(1) << 7) #define CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN (ULL(1) << 53) /******************************************************************************* diff --git a/include/lib/cpus/aarch64/cortex_x2.h b/include/lib/cpus/aarch64/cortex_x2.h index 9ec51775e..45163392f 100644 --- a/include/lib/cpus/aarch64/cortex_x2.h +++ b/include/lib/cpus/aarch64/cortex_x2.h @@ -18,15 +18,6 @@ #define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4 #define CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) -/******************************************************************************* - * CPU Extended Control register 2 specific definitions - ******************************************************************************/ -#define CORTEX_X2_CPUECTLR2_EL1 S3_0_C15_C1_5 - -#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT U(11) -#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) -#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9) - /******************************************************************************* * CPU Auxiliary Control register 3 specific definitions. ******************************************************************************/ diff --git a/include/lib/cpus/aarch64/cortex_x3.h b/include/lib/cpus/aarch64/cortex_x3.h index 8834db118..2869ec84a 100644 --- a/include/lib/cpus/aarch64/cortex_x3.h +++ b/include/lib/cpus/aarch64/cortex_x3.h @@ -48,15 +48,6 @@ ******************************************************************************/ #define CORTEX_X3_CPUACTLR6_EL1 S3_0_C15_C8_1 -/******************************************************************************* - * CPU Extended Control register 2 specific definitions. - ******************************************************************************/ -#define CORTEX_X3_CPUECTLR2_EL1 S3_0_C15_C1_5 - -#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB U(11) -#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) -#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9) - /******************************************************************************* * CPU Auxiliary Control register 3 specific definitions. ******************************************************************************/ diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h index f5837d4fb..e4487c4ce 100644 --- a/include/lib/cpus/aarch64/neoverse_n2.h +++ b/include/lib/cpus/aarch64/neoverse_n2.h @@ -62,9 +62,6 @@ * CPU Auxiliary Control register specific definitions. ******************************************************************************/ #define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5 -#define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) -#define CPUECTLR2_EL1_PF_MODE_LSB U(11) -#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) #define CPUECTLR2_EL1_TXREQ_STATIC_FULL ULL(0) #define CPUECTLR2_EL1_TXREQ_LSB U(0) #define CPUECTLR2_EL1_TXREQ_WIDTH U(3) diff --git a/include/lib/cpus/aarch64/neoverse_v1.h b/include/lib/cpus/aarch64/neoverse_v1.h index 1e2d7eaf9..bbba2a7f4 100644 --- a/include/lib/cpus/aarch64/neoverse_v1.h +++ b/include/lib/cpus/aarch64/neoverse_v1.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2023, Arm Limited. All rights reserved. + * Copyright (c) 2019-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,9 +22,6 @@ #define NEOVERSE_V1_CPUPCR_EL3 S3_6_C15_C8_1 #define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) #define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) -#define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3) -#define CPUECTLR_EL1_PF_MODE_LSB U(6) -#define CPUECTLR_EL1_PF_MODE_WIDTH U(2) /******************************************************************************* * CPU Power Control register specific definitions diff --git a/include/lib/cpus/aarch64/neoverse_v2.h b/include/lib/cpus/aarch64/neoverse_v2.h index 427cafa86..cdbe2bbf5 100644 --- a/include/lib/cpus/aarch64/neoverse_v2.h +++ b/include/lib/cpus/aarch64/neoverse_v2.h @@ -32,9 +32,6 @@ * CPU Extended Control register 2 specific definitions. ******************************************************************************/ #define NEOVERSE_V2_CPUECTLR2_EL1 S3_0_C15_C1_5 -#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) -#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB U(11) -#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) #define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL ULL(0) #define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB U(0) #define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH U(3) diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S index 23f785047..54bb45348 100644 --- a/lib/cpus/aarch64/cortex_a710.S +++ b/lib/cpus/aarch64/cortex_a710.S @@ -87,13 +87,6 @@ workaround_reset_end cortex_a710, ERRATUM(2055002) check_erratum_range cortex_a710, ERRATUM(2055002), CPU_REV(1, 0), CPU_REV(2, 0) -workaround_reset_start cortex_a710, ERRATUM(2058056), ERRATA_A710_2058056 - sysreg_bitfield_insert CORTEX_A710_CPUECTLR2_EL1, CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV, \ - CPUECTLR2_EL1_PF_MODE_LSB, CPUECTLR2_EL1_PF_MODE_WIDTH -workaround_reset_end cortex_a710, ERRATUM(2058056) - -check_erratum_ls cortex_a710, ERRATUM(2058056), CPU_REV(2, 1) - workaround_reset_start cortex_a710, ERRATUM(2081180), ERRATA_A710_2081180 ldr x0,=0x3 msr S3_6_c15_c8_0,x0 diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S index 36b0a04c0..b166823f1 100644 --- a/lib/cpus/aarch64/cortex_a78.S +++ b/lib/cpus/aarch64/cortex_a78.S @@ -99,16 +99,6 @@ workaround_reset_end cortex_a78, ERRATUM(1952683) check_erratum_ls cortex_a78, ERRATUM(1952683), CPU_REV(0, 0) -workaround_reset_start cortex_a78, ERRATUM(2132060), ERRATA_A78_2132060 - /* Apply the workaround. */ - mrs x1, CORTEX_A78_CPUECTLR_EL1 - mov x0, #CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV - bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH - msr CORTEX_A78_CPUECTLR_EL1, x1 -workaround_reset_end cortex_a78, ERRATUM(2132060) - -check_erratum_ls cortex_a78, ERRATUM(2132060), CPU_REV(1, 2) - workaround_reset_start cortex_a78, ERRATUM(2242635), ERRATA_A78_2242635 ldr x0, =0x5 msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */ diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S index 8f2dea880..19d988e9f 100644 --- a/lib/cpus/aarch64/cortex_a78c.S +++ b/lib/cpus/aarch64/cortex_a78c.S @@ -37,18 +37,6 @@ workaround_reset_end cortex_a78c, ERRATUM(1827440) check_erratum_ls cortex_a78c, ERRATUM(1827440), CPU_REV(0, 0) -workaround_reset_start cortex_a78c, ERRATUM(2132064), ERRATA_A78C_2132064 - /* -------------------------------------------------------- - * Place the data prefetcher in the most conservative mode - * to reduce prefetches by writing the following bits to - * the value indicated: ecltr[7:6], PF_MODE = 2'b11 - * -------------------------------------------------------- - */ - sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, (CORTEX_A78C_CPUECTLR_EL1_BIT_6 | CORTEX_A78C_CPUECTLR_EL1_BIT_7) -workaround_reset_end cortex_a78c, ERRATUM(2132064) - -check_erratum_range cortex_a78c, ERRATUM(2132064), CPU_REV(0, 1), CPU_REV(0, 2) - workaround_reset_start cortex_a78c, ERRATUM(2242638), ERRATA_A78C_2242638 ldr x0, =0x5 msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S index ccdd3b87e..910a6a9bc 100644 --- a/lib/cpus/aarch64/cortex_x2.S +++ b/lib/cpus/aarch64/cortex_x2.S @@ -50,13 +50,6 @@ workaround_reset_end cortex_x2, ERRATUM(2017096) check_erratum_ls cortex_x2, ERRATUM(2017096), CPU_REV(2, 0) -workaround_reset_start cortex_x2, ERRATUM(2058056), ERRATA_X2_2058056 - sysreg_bitfield_insert CORTEX_X2_CPUECTLR2_EL1, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV, \ - CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH -workaround_reset_end cortex_x2, ERRATUM(2058056) - -check_erratum_ls cortex_x2, ERRATUM(2058056), CPU_REV(2, 1) - workaround_reset_start cortex_x2, ERRATUM(2081180), ERRATA_X2_2081180 /* Apply instruction patching sequence */ ldr x0, =0x3 diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S index 628642b80..c4872fe55 100644 --- a/lib/cpus/aarch64/cortex_x3.S +++ b/lib/cpus/aarch64/cortex_x3.S @@ -30,13 +30,6 @@ cpu_reset_prologue cortex_x3 -workaround_reset_start cortex_x3, ERRATUM(2070301), ERRATA_X3_2070301 - sysreg_bitfield_insert CORTEX_X3_CPUECTLR2_EL1, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV, \ - CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH -workaround_reset_end cortex_x3, ERRATUM(2070301) - -check_erratum_ls cortex_x3, ERRATUM(2070301), CPU_REV(1, 2) - workaround_reset_start cortex_x3, ERRATUM(2266875), ERRATA_X3_2266875 sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(22) workaround_reset_end cortex_x3, ERRATUM(2266875) diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S index 4f1d53dc5..7d9d7f15e 100644 --- a/lib/cpus/aarch64/neoverse_n2.S +++ b/lib/cpus/aarch64/neoverse_n2.S @@ -79,16 +79,6 @@ workaround_reset_end neoverse_n2, ERRATUM(2067956) check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0) -workaround_reset_start neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953 - /* Apply instruction patching sequence */ - mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 - mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV - bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH - msr NEOVERSE_N2_CPUECTLR2_EL1, x1 -workaround_reset_end neoverse_n2, ERRATUM(2138953) - -check_erratum_ls neoverse_n2, ERRATUM(2138953), CPU_REV(0, 3) - workaround_reset_start neoverse_n2, ERRATUM(2138956), ERRATA_N2_2138956 /* Apply instruction patching sequence */ ldr x0,=0x3 diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S index a3b05e126..f975be008 100644 --- a/lib/cpus/aarch64/neoverse_v1.S +++ b/lib/cpus/aarch64/neoverse_v1.S @@ -156,15 +156,6 @@ workaround_reset_end neoverse_v1, ERRATUM(1966096) check_erratum_range neoverse_v1, ERRATUM(1966096), CPU_REV(1, 0), CPU_REV(1, 1) -workaround_reset_start neoverse_v1, ERRATUM(2108267), ERRATA_V1_2108267 - mrs x1, NEOVERSE_V1_CPUECTLR_EL1 - mov x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV - bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH - msr NEOVERSE_V1_CPUECTLR_EL1, x1 -workaround_reset_end neoverse_v1, ERRATUM(2108267) - -check_erratum_ls neoverse_v1, ERRATUM(2108267), CPU_REV(1, 2) - workaround_reset_start neoverse_v1, ERRATUM(2139242), ERRATA_V1_2139242 mov x0, #0x3 msr S3_6_C15_C8_0, x0 diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S index a320d4452..ce84942f3 100644 --- a/lib/cpus/aarch64/neoverse_v2.S +++ b/lib/cpus/aarch64/neoverse_v2.S @@ -24,13 +24,6 @@ cpu_reset_prologue neoverse_v2 -workaround_reset_start neoverse_v2, ERRATUM(2331132), ERRATA_V2_2331132 - sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV, \ - NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH -workaround_reset_end neoverse_v2, ERRATUM(2331132) - -check_erratum_ls neoverse_v2, ERRATUM(2331132), CPU_REV(0, 2) - workaround_reset_start neoverse_v2, ERRATUM(2618597), ERRATA_V2_2618597 /* Disable retention control for WFI and WFE. */ mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 4cfa765ff..4b8de0054 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -315,10 +315,6 @@ CPU_FLAG_LIST += ERRATA_A78_1821534 # to revision r0p0 of the A78 cpu and was fixed in the revision r1p0. CPU_FLAG_LIST += ERRATA_A78_1952683 -# Flag to apply erratum 2132060 workaround during reset. This erratum applies -# to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu. It is still open. -CPU_FLAG_LIST += ERRATA_A78_2132060 - # Flag to apply erratum 2242635 workaround during reset. This erratum applies # to revisions r1p0, r1p1, and r1p2 of the A78 cpu and is open. The issue is # present in r0p0 as well but there is no workaround for that revision. @@ -380,10 +376,6 @@ CPU_FLAG_LIST += ERRATA_A78C_1827440 # It is still open. CPU_FLAG_LIST += ERRATA_A78_AE_2712574 -# Flag to apply erratum 2132064 workaround during reset. This erratum applies -# to revisions r0p1 and r0p2 of the A78C cpu. It is still open. -CPU_FLAG_LIST += ERRATA_A78C_2132064 - # Flag to apply erratum 2242638 workaround during reset. This erratum applies # to revisions r0p1 and r0p2 of the A78C cpu. It is still open. CPU_FLAG_LIST += ERRATA_A78C_2242638 @@ -523,10 +515,6 @@ CPU_FLAG_LIST += ERRATA_V1_1966096 # to revisions r0p0, r1p0, and r1p1 of the Neoverse V1 cpu and is still open. CPU_FLAG_LIST += ERRATA_V1_2139242 -# Flag to apply erratum 2108267 workaround during reset. This erratum applies -# to revisions r0p0, r1p0, and r1p1 of the Neoverse V1 cpu and is still open. -CPU_FLAG_LIST += ERRATA_V1_2108267 - # Flag to apply erratum 2216392 workaround during reset. This erratum applies # to revisions r1p0 and r1p1 of the Neoverse V1 cpu and is still open. This # issue exists in r0p0 as well but there is no workaround for that revision. @@ -585,11 +573,6 @@ CPU_FLAG_LIST += ERRATA_A710_2081180 # to revision r2p0 of the Cortex-A710 cpu and is still open. CPU_FLAG_LIST += ERRATA_A710_2083908 -# Flag to apply erratum 2058056 workaround during reset. This erratum applies -# to revisions r0p0, r1p0, r2p0 and r2p1 of the Cortex-A710 cpu and is still -# open. -CPU_FLAG_LIST += ERRATA_A710_2058056 - # Flag to apply erratum 2055002 workaround during reset. This erratum applies # to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open. CPU_FLAG_LIST += ERRATA_A710_2055002 @@ -680,10 +663,6 @@ CPU_FLAG_LIST += ERRATA_N2_2189731 # to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1. CPU_FLAG_LIST += ERRATA_N2_2138956 -# Flag to apply erratum 2138953 workaround during reset. This erratum applies -# to revision r0p0, r0p1, r0p2, r0p3 of the Neoverse N2 cpu and is still open. -CPU_FLAG_LIST += ERRATA_N2_2138953 - # Flag to apply erratum 2242415 workaround during reset. This erratum applies # to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1. CPU_FLAG_LIST += ERRATA_N2_2242415 @@ -751,10 +730,6 @@ CPU_FLAG_LIST += ERRATA_N3_3699563 # to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open. CPU_FLAG_LIST += ERRATA_X2_2002765 -# Flag to apply erratum 2058056 workaround during reset. This erratum applies -# to revisions r0p0, r1p0, r2p0 and r2p1 of the Cortex-X2 cpu and is still open. -CPU_FLAG_LIST += ERRATA_X2_2058056 - # Flag to apply erratum 2083908 workaround during reset. This erratum applies # to revision r2p0 of the Cortex-X2 cpu and is still open. CPU_FLAG_LIST += ERRATA_X2_2083908 @@ -810,11 +785,6 @@ CPU_FLAG_LIST += ERRATA_X2_2778471 # of the Cortex-X2 cpu and is still open. CPU_FLAG_LIST += ERRATA_X2_3701772 -# Flag to apply erratum 2070301 workaround on reset. This erratum applies -# to revisions r0p0, r1p0, r1p1 and r1p2 of the Cortex-X3 cpu and is -# still open. -CPU_FLAG_LIST += ERRATA_X3_2070301 - # Flag to apply erratum 2266875 workaround during reset. This erratum applies # to revisions r0p0 and r1p0 of the Cortex-X3 cpu, it is fixed in r1p1. CPU_FLAG_LIST += ERRATA_X3_2266875 @@ -983,10 +953,6 @@ CPU_FLAG_LIST += ERRATA_A520_2858100 # applies to revision r0p0 and r0p1 of the Cortex-A520 cpu and is fixed in r0p2. CPU_FLAG_LIST += ERRATA_A520_2938996 -# Flag to apply erratum 2331132 workaround during reset. This erratum applies -# to revisions r0p0, r0p1 and r0p2. It is still open. -CPU_FLAG_LIST += ERRATA_V2_2331132 - # Flag to apply erratum 2618597 workaround during reset. This erratum applies # to revisions r0p0 and r0p1. It is fixed in r0p2. CPU_FLAG_LIST += ERRATA_V2_2618597 diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk b/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk index 577694895..421c14ead 100644 --- a/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk +++ b/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk @@ -125,7 +125,6 @@ ERRATA_N2_2067956 := 1 ERRATA_N2_2025414 := 1 ERRATA_N2_2189731 := 1 ERRATA_N2_2138956 := 1 -ERRATA_N2_2138953 := 1 ERRATA_N2_2242415 := 1 ERRATA_N2_2138958 := 1 ERRATA_N2_2242400 := 1 diff --git a/plat/mediatek/mt8188/plat_config.mk b/plat/mediatek/mt8188/plat_config.mk index 82ef7e8f4..3f7d1871e 100644 --- a/plat/mediatek/mt8188/plat_config.mk +++ b/plat/mediatek/mt8188/plat_config.mk @@ -27,7 +27,6 @@ ERRATA_A78_1688305 := 1 ERRATA_A78_1941498 := 1 ERRATA_A78_1951500 := 1 ERRATA_A78_1821534 := 1 -ERRATA_A78_2132060 := 1 ERRATA_A78_2242635 := 1 ERRATA_A78_2376745 := 1 ERRATA_A78_2395406 := 1 diff --git a/plat/mediatek/mt8195/platform.mk b/plat/mediatek/mt8195/platform.mk index 48dafa3cd..e604d4f8d 100644 --- a/plat/mediatek/mt8195/platform.mk +++ b/plat/mediatek/mt8195/platform.mk @@ -99,7 +99,6 @@ ERRATA_A78_1688305 := 1 ERRATA_A78_1941498 := 1 ERRATA_A78_1951500 := 1 ERRATA_A78_1821534 := 1 -ERRATA_A78_2132060 := 1 ERRATA_A78_2242635 := 1 # indicate the reset vector address can be programmed diff --git a/plat/qti/sc7280/platform.mk b/plat/qti/sc7280/platform.mk index 3d7d72883..0b5ae5203 100644 --- a/plat/qti/sc7280/platform.mk +++ b/plat/qti/sc7280/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved. # Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause @@ -20,7 +20,6 @@ HW_ASSISTED_COHERENCY := 1 ERRATA_A55_1530923 := 1 ERRATA_A78_1941498 := 1 ERRATA_A78_1951500 := 1 -ERRATA_A78_2132060 := 1 # Disable the PSCI platform compatibility layer ENABLE_PLAT_COMPAT := 0