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Add support for Cortex-Ares and Cortex-A76 CPUs

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Both Cortex-Ares and Cortex-A76 CPUs use the ARM DynamIQ Shared Unit
(DSU).  The power-down and power-up sequences are therefore mostly
managed in hardware, and required software operations are simple.

Change-Id: I3a9447b5bdbdbc5ed845b20f6564d086516fa161
Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
This commit is contained in:
Isla Mitchell 2017-08-03 16:04:46 +01:00 • committed by Dimitris Papastamos
parent 83685de911
commit abbffe98ed
5 changed files with 149 additions and 1 deletions
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22
include/lib/cpus/aarch64/cortex_a76.h Normal file
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@ -0,0 +1,22 @@
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_A76_H__
#define __CORTEX_A76_H__
/* Cortex-A76 MIDR for revision 0 */
#define CORTEX_A76_MIDR 0x410fd0b0
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
#define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4
/* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */
#define CORTEX_A76_CORE_PWRDN_EN_MASK 0x1
#endif /* __CORTEX_A76_H__ */

22
include/lib/cpus/aarch64/cortex_ares.h Normal file
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@ -0,0 +1,22 @@
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_ARES_H__
#define __CORTEX_ARES_H__
/* Cortex-ARES MIDR for revision 0 */
#define CORTEX_ARES_MIDR 0x410fd0c0
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
#define CORTEX_ARES_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_ARES_CPUECTLR_EL1 S3_0_C15_C1_4
/* Definitions of register field mask in CORTEX_ARES_CPUPWRCTLR_EL1 */
#define CORTEX_ARES_CORE_PWRDN_EN_MASK 0x1
#endif /* __CORTEX_ARES_H__ */

51
lib/cpus/aarch64/cortex_a76.S Normal file
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@ -0,0 +1,51 @@
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <bl_common.h>
#include <cortex_a76.h>
#include <cpu_macros.S>
#include <plat_macros.S>
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
*/
func cortex_a76_core_pwr_dwn
/* ---------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
mrs x0, CORTEX_A76_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_A76_CORE_PWRDN_EN_MASK
msr CORTEX_A76_CPUPWRCTLR_EL1, x0
isb
ret
endfunc cortex_a76_core_pwr_dwn
/* ---------------------------------------------
* This function provides cortex_a76 specific
* register information for crash reporting.
* It needs to return with x6 pointing to
* a list of register names in ascii and
* x8 - x15 having values of registers to be
* reported.
* ---------------------------------------------
*/
.section .rodata.cortex_a76_regs, "aS"
cortex_a76_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
func cortex_a76_cpu_reg_dump
adr x6, cortex_a76_regs
mrs x8, CORTEX_A76_CPUECTLR_EL1
ret
endfunc cortex_a76_cpu_reg_dump
declare_cpu_ops cortex_a76, CORTEX_A76_MIDR, \
CPU_NO_RESET_FUNC, \
cortex_a76_core_pwr_dwn

51
lib/cpus/aarch64/cortex_ares.S Normal file
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@ -0,0 +1,51 @@
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <bl_common.h>
#include <cortex_ares.h>
#include <cpu_macros.S>
#include <plat_macros.S>
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
*/
func cortex_ares_core_pwr_dwn
/* ---------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
mrs x0, CORTEX_ARES_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_ARES_CORE_PWRDN_EN_MASK
msr CORTEX_ARES_CPUPWRCTLR_EL1, x0
isb
ret
endfunc cortex_ares_core_pwr_dwn
/* ---------------------------------------------
* This function provides cortex_ares specific
* register information for crash reporting.
* It needs to return with x6 pointing to
* a list of register names in ascii and
* x8 - x15 having values of registers to be
* reported.
* ---------------------------------------------
*/
.section .rodata.cortex_ares_regs, "aS"
cortex_ares_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
func cortex_ares_cpu_reg_dump
adr x6, cortex_ares_regs
mrs x8, CORTEX_ARES_CPUECTLR_EL1
ret
endfunc cortex_ares_cpu_reg_dump
declare_cpu_ops cortex_ares, CORTEX_ARES_MIDR, \
CPU_NO_RESET_FUNC, \
cortex_ares_core_pwr_dwn

4
plat/arm/board/fvp/platform.mk
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@ -114,7 +114,9 @@ FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
lib/cpus/aarch64/cortex_a57.S \
lib/cpus/aarch64/cortex_a72.S \
lib/cpus/aarch64/cortex_a73.S \
lib/cpus/aarch64/cortex_a75.S
lib/cpus/aarch64/cortex_a75.S \
lib/cpus/aarch64/cortex_a76.S \
lib/cpus/aarch64/cortex_ares.S
else
FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S
endif