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refactor(plat/allwinner): map SRAM as device memory by default

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The SRAM on Allwinner platforms is shared between BL31 and coprocessor
firmware. Previously, SRAM was mapped as normal memory by default.
This scheme requires carveouts and cache maintenance code for proper
synchronization with the coprocessor.

A better scheme is to only map pages owned by BL31 as normal memory,
and leave everything else as device memory. This removes the need for
cache maintenance, and it makes the mapping for BL31 RW data explicit
instead of magic.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I820ddeba2dfa2396361c2322308c0db51b55c348
This commit is contained in:
Samuel Holland 2020-12-13 20:45:49 -06:00
parent bc135624ef
commit ab74206b60
4 changed files with 14 additions and 8 deletions
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4
plat/allwinner/common/include/platform_def.h
View file

@ -52,8 +52,8 @@
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
#define MAX_STATIC_MMAP_REGIONS 5
#define MAX_MMAP_REGIONS (3 + MAX_STATIC_MMAP_REGIONS)
#define MAX_STATIC_MMAP_REGIONS 4
#define MAX_MMAP_REGIONS (5 + MAX_STATIC_MMAP_REGIONS)
#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE \
(SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE - 0x200)

16
plat/allwinner/common/sunxi_common.c
View file

@ -16,11 +16,7 @@
static const mmap_region_t sunxi_mmap[MAX_STATIC_MMAP_REGIONS + 1] = {
MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE,
MT_RW_DATA | MT_SECURE),
#ifdef SUNXI_SCP_BASE
MAP_REGION_FLAT(SUNXI_SCP_BASE, SUNXI_SCP_SIZE,
MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
#endif
MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE,
MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE,
@ -40,12 +36,24 @@ void sunxi_configure_mmu_el3(int flags)
mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
BL_CODE_END - BL_CODE_BASE,
MT_CODE | MT_SECURE);
mmap_add_region(BL_CODE_END, BL_CODE_END,
BL_END - BL_CODE_END,
MT_RW_DATA | MT_SECURE);
#if SEPARATE_CODE_AND_RODATA
mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE,
BL_RO_DATA_END - BL_RO_DATA_BASE,
MT_RO_DATA | MT_SECURE);
#endif
#if SEPARATE_NOBITS_REGION
mmap_add_region(BL_NOBITS_BASE, BL_NOBITS_BASE,
BL_NOBITS_END - BL_NOBITS_BASE,
MT_RW_DATA | MT_SECURE);
#endif
#if USE_COHERENT_MEM
mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER);
#endif
mmap_add(sunxi_mmap);
init_xlat_tables();

1
plat/allwinner/common/sunxi_scpi_pm.c
View file

@ -212,7 +212,6 @@ int sunxi_set_scpi_psci_ops(const plat_psci_ops_t **psci_ops)
uint32_t offset = SUNXI_SCP_BASE - vector;
mmio_write_32(vector, offset >> 2);
clean_dcache_range(vector, sizeof(uint32_t));
}
/* Take the SCP out of reset. */

1
plat/allwinner/sun50i_a64/sunxi_power.c
View file

@ -244,7 +244,6 @@ void sunxi_cpu_power_off_self(void)
* in instruction granularity (32 bits).
*/
mmio_write_32(arisc_reset_vec, ((uintptr_t)code - arisc_reset_vec) / 4);
clean_dcache_range(arisc_reset_vec, 4);
/* De-assert the arisc reset line to let it run. */
mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0));