mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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Merge changes I50721040,I1ce4b7b4,I9658aef7,I40ff55eb into integration
* changes: fix(intel): remove unused printout fix(intel): fix configuration status based on start request style(intel): align the sequence in header file fix(intel): remove redundant NOC header declarations
This commit is contained in:
Joanna Farley
TrustedFirmware Code Review
commit
aa69de86f0
6 changed files with 61 additions and 173 deletions
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@ -1,69 +0,0 @@
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/*
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* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef AGX_NOC_H
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#define AGX_NOC_H
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#define AXI_AP (1<<0)
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#define FPGA2SOC (1<<16)
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#define MPU (1<<24)
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#define AGX_NOC_PER_SCR_NAND 0xffd21000
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#define AGX_NOC_PER_SCR_NAND_DATA 0xffd21004
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#define AGX_NOC_PER_SCR_USB0 0xffd2100c
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#define AGX_NOC_PER_SCR_USB1 0xffd21010
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#define AGX_NOC_PER_SCR_SPI_M0 0xffd2101c
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#define AGX_NOC_PER_SCR_SPI_M1 0xffd21020
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#define AGX_NOC_PER_SCR_SPI_S0 0xffd21024
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#define AGX_NOC_PER_SCR_SPI_S1 0xffd21028
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#define AGX_NOC_PER_SCR_EMAC0 0xffd2102c
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#define AGX_NOC_PER_SCR_EMAC1 0xffd21030
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#define AGX_NOC_PER_SCR_EMAC2 0xffd21034
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#define AGX_NOC_PER_SCR_SDMMC 0xffd21040
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#define AGX_NOC_PER_SCR_GPIO0 0xffd21044
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#define AGX_NOC_PER_SCR_GPIO1 0xffd21048
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#define AGX_NOC_PER_SCR_I2C0 0xffd21050
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#define AGX_NOC_PER_SCR_I2C1 0xffd21058
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#define AGX_NOC_PER_SCR_I2C2 0xffd2105c
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#define AGX_NOC_PER_SCR_I2C3 0xffd21060
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#define AGX_NOC_PER_SCR_SP_TIMER0 0xffd21064
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#define AGX_NOC_PER_SCR_SP_TIMER1 0xffd21068
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#define AGX_NOC_PER_SCR_UART0 0xffd2106c
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#define AGX_NOC_PER_SCR_UART1 0xffd21070
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#define AGX_NOC_SYS_SCR_DMA_ECC 0xffd21108
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#define AGX_NOC_SYS_SCR_EMAC0RX_ECC 0xffd2110c
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#define AGX_NOC_SYS_SCR_EMAC0TX_ECC 0xffd21110
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#define AGX_NOC_SYS_SCR_EMAC1RX_ECC 0xffd21114
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#define AGX_NOC_SYS_SCR_EMAC1TX_ECC 0xffd21118
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#define AGX_NOC_SYS_SCR_EMAC2RX_ECC 0xffd2111c
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#define AGX_NOC_SYS_SCR_EMAC2TX_ECC 0xffd21120
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#define AGX_NOC_SYS_SCR_NAND_ECC 0xffd2112c
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#define AGX_NOC_SYS_SCR_NAND_READ_ECC 0xffd21130
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#define AGX_NOC_SYS_SCR_NAND_WRITE_ECC 0xffd21134
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#define AGX_NOC_SYS_SCR_OCRAM_ECC 0xffd21138
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#define AGX_NOC_SYS_SCR_SDMMC_ECC 0xffd21140
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#define AGX_NOC_SYS_SCR_USB0_ECC 0xffd21144
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#define AGX_NOC_SYS_SCR_USB1_ECC 0xffd21148
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#define AGX_NOC_SYS_SCR_CLK_MGR 0xffd2114c
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#define AGX_NOC_SYS_SCR_IO_MGR 0xffd21154
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#define AGX_NOC_SYS_SCR_RST_MGR 0xffd21158
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#define AGX_NOC_SYS_SCR_SYS_MGR 0xffd2115c
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#define AGX_NOC_SYS_SCR_OSC0_TIMER 0xffd21160
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#define AGX_NOC_SYS_SCR_OSC1_TIMER 0xffd21164
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#define AGX_NOC_SYS_SCR_WATCHDOG0 0xffd21168
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#define AGX_NOC_SYS_SCR_WATCHDOG1 0xffd2116c
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#define AGX_NOC_SYS_SCR_WATCHDOG2 0xffd21170
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#define AGX_NOC_SYS_SCR_WATCHDOG3 0xffd21174
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#define AGX_NOC_SYS_SCR_DAP 0xffd21178
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#define AGX_NOC_SYS_SCR_L4_NOC_PROBES 0xffd21190
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#define AGX_NOC_SYS_SCR_L4_NOC_QOS 0xffd21194
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#define AGX_CCU_NOC_BRIDGE_CPU0_RAM 0xf7004688
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#define AGX_CCU_NOC_BRIDGE_IOM_RAM 0xf7004688
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#endif
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@ -180,6 +180,12 @@ struct fpga_config_info {
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int block_number;
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};
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typedef enum {
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NO_REQUEST = 0,
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RECONFIGURATION,
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BITSTREAM_AUTH
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} config_type;
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/* Function Definitions */
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bool is_size_4_bytes_aligned(uint32_t size);
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bool is_address_in_ddr_range(uint64_t addr, uint64_t size);
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@ -315,36 +315,6 @@ uint32_t intel_fcs_decryption(uint32_t src_addr, uint32_t src_size,
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return INTEL_SIP_SMC_STATUS_OK;
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}
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uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size,
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uint32_t *mbox_error)
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{
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int status;
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unsigned int resp_len = FCS_SHA384_WORD_SIZE;
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if (!is_address_in_ddr_range(addr, FCS_SHA384_BYTE_SIZE)) {
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return INTEL_SIP_SMC_STATUS_REJECTED;
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}
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status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_GET_ROM_PATCH_SHA384, NULL, 0U,
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CMD_CASUAL, (uint32_t *) addr, &resp_len);
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if (status < 0) {
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*mbox_error = -status;
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return INTEL_SIP_SMC_STATUS_ERROR;
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}
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if (resp_len != FCS_SHA384_WORD_SIZE) {
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*mbox_error = GENERIC_RESPONSE_ERROR;
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return INTEL_SIP_SMC_STATUS_ERROR;
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}
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*ret_size = FCS_SHA384_BYTE_SIZE;
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flush_dcache_range(addr, *ret_size);
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return INTEL_SIP_SMC_STATUS_OK;
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}
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int intel_fcs_encryption_ext(uint32_t session_id, uint32_t context_id,
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uint32_t src_addr, uint32_t src_size,
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uint32_t dst_addr, uint32_t *dst_size, uint32_t *mbox_error)
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@ -561,6 +531,36 @@ int intel_fcs_get_measurement(uint64_t src_addr, uint32_t src_size,
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return INTEL_SIP_SMC_STATUS_OK;
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}
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uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size,
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uint32_t *mbox_error)
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{
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int status;
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unsigned int resp_len = FCS_SHA384_WORD_SIZE;
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if (!is_address_in_ddr_range(addr, FCS_SHA384_BYTE_SIZE)) {
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return INTEL_SIP_SMC_STATUS_REJECTED;
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}
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status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_GET_ROM_PATCH_SHA384, NULL, 0U,
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CMD_CASUAL, (uint32_t *) addr, &resp_len);
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if (status < 0) {
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*mbox_error = -status;
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return INTEL_SIP_SMC_STATUS_ERROR;
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}
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if (resp_len != FCS_SHA384_WORD_SIZE) {
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*mbox_error = GENERIC_RESPONSE_ERROR;
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return INTEL_SIP_SMC_STATUS_ERROR;
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}
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*ret_size = FCS_SHA384_BYTE_SIZE;
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flush_dcache_range(addr, *ret_size);
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return INTEL_SIP_SMC_STATUS_OK;
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}
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int intel_fcs_get_attestation_cert(uint32_t cert_request, uint64_t dst_addr,
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uint32_t *dst_size, uint32_t *mbox_error)
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{
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@ -36,7 +36,6 @@ void socfpga_delay_timer_init_args(void)
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timer_init(&plat_timer_ops);
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NOTICE("BL31: MPU clock frequency: %d MHz\n", plat_timer_ops.clk_div);
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}
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void socfpga_delay_timer_init(void)
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@ -19,6 +19,7 @@
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/* Total buffer the driver can hold */
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#define FPGA_CONFIG_BUFFER_SIZE 4
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static config_type request_type = NO_REQUEST;
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static int current_block, current_buffer;
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static int read_block, max_blocks;
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static uint32_t send_id, rcv_id;
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@ -27,10 +28,8 @@ static bool bridge_disable;
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/* RSU static variables */
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static uint32_t rsu_dcmf_ver[4] = {0};
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/* RSU Max Retry */
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static uint32_t rsu_max_retry;
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static uint16_t rsu_dcmf_stat[4] = {0};
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static uint32_t rsu_max_retry;
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/* SiP Service UUID */
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DEFINE_SVC_UUID2(intl_svc_uid,
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@ -89,28 +88,39 @@ static int intel_fpga_sdm_write_all(void)
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return 0;
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}
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static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type)
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static uint32_t intel_mailbox_fpga_config_isdone(void)
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{
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uint32_t ret;
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if (query_type == 1U) {
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ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, false);
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} else {
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ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true);
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switch (request_type) {
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case RECONFIGURATION:
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ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS,
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true);
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break;
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case BITSTREAM_AUTH:
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ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS,
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false);
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break;
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default:
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ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS,
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false);
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break;
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}
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if (ret != 0U) {
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if (ret == MBOX_CFGSTAT_STATE_CONFIG) {
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return INTEL_SIP_SMC_STATUS_BUSY;
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} else {
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request_type = NO_REQUEST;
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return INTEL_SIP_SMC_STATUS_ERROR;
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}
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}
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if (bridge_disable) {
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if (bridge_disable != 0U) {
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socfpga_bridges_enable(~0); /* Enable bridge */
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bridge_disable = false;
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}
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request_type = NO_REQUEST;
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return INTEL_SIP_SMC_STATUS_OK;
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}
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@ -169,6 +179,7 @@ static int intel_fpga_config_completed_write(uint32_t *completed_addr,
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if (status != MBOX_NO_RESPONSE &&
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status != MBOX_TIMEOUT && resp_len != 0) {
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mailbox_clear_response();
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request_type = NO_REQUEST;
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return INTEL_SIP_SMC_STATUS_ERROR;
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}
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@ -205,6 +216,8 @@ static int intel_fpga_config_start(uint32_t flag)
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unsigned int size = 0;
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unsigned int resp_len = ARRAY_SIZE(response);
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request_type = RECONFIGURATION;
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if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) {
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bridge_disable = true;
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}
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@ -212,6 +225,7 @@ static int intel_fpga_config_start(uint32_t flag)
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if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) {
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size = 1;
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bridge_disable = false;
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request_type = BITSTREAM_AUTH;
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}
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mailbox_clear_response();
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@ -224,6 +238,7 @@ static int intel_fpga_config_start(uint32_t flag)
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if (status < 0) {
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bridge_disable = false;
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request_type = NO_REQUEST;
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return INTEL_SIP_SMC_STATUS_ERROR;
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}
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@ -644,7 +659,7 @@ uintptr_t sip_smc_handler_v1(uint32_t smc_fid,
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SMC_UUID_RET(handle, intl_svc_uid);
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case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE:
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status = intel_mailbox_fpga_config_isdone(x1);
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status = intel_mailbox_fpga_config_isdone();
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SMC_RET4(handle, status, 0, 0, 0);
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case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM:
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@ -1,63 +0,0 @@
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/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#define AXI_AP (1<<0)
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#define FPGA2SOC (1<<16)
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#define MPU (1<<24)
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#define S10_NOC_PER_SCR_NAND 0xffd21000
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#define S10_NOC_PER_SCR_NAND_DATA 0xffd21004
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#define S10_NOC_PER_SCR_USB0 0xffd2100c
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#define S10_NOC_PER_SCR_USB1 0xffd21010
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#define S10_NOC_PER_SCR_SPI_M0 0xffd2101c
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#define S10_NOC_PER_SCR_SPI_M1 0xffd21020
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#define S10_NOC_PER_SCR_SPI_S0 0xffd21024
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#define S10_NOC_PER_SCR_SPI_S1 0xffd21028
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#define S10_NOC_PER_SCR_EMAC0 0xffd2102c
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#define S10_NOC_PER_SCR_EMAC1 0xffd21030
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#define S10_NOC_PER_SCR_EMAC2 0xffd21034
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#define S10_NOC_PER_SCR_SDMMC 0xffd21040
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#define S10_NOC_PER_SCR_GPIO0 0xffd21044
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#define S10_NOC_PER_SCR_GPIO1 0xffd21048
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#define S10_NOC_PER_SCR_I2C0 0xffd21050
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#define S10_NOC_PER_SCR_I2C1 0xffd21058
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#define S10_NOC_PER_SCR_I2C2 0xffd2105c
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#define S10_NOC_PER_SCR_I2C3 0xffd21060
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#define S10_NOC_PER_SCR_SP_TIMER0 0xffd21064
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#define S10_NOC_PER_SCR_SP_TIMER1 0xffd21068
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#define S10_NOC_PER_SCR_UART0 0xffd2106c
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#define S10_NOC_PER_SCR_UART1 0xffd21070
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#define S10_NOC_SYS_SCR_DMA_ECC 0xffd21108
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#define S10_NOC_SYS_SCR_EMAC0RX_ECC 0xffd2110c
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#define S10_NOC_SYS_SCR_EMAC0TX_ECC 0xffd21110
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#define S10_NOC_SYS_SCR_EMAC1RX_ECC 0xffd21114
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#define S10_NOC_SYS_SCR_EMAC1TX_ECC 0xffd21118
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#define S10_NOC_SYS_SCR_EMAC2RX_ECC 0xffd2111c
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#define S10_NOC_SYS_SCR_EMAC2TX_ECC 0xffd21120
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#define S10_NOC_SYS_SCR_NAND_ECC 0xffd2112c
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#define S10_NOC_SYS_SCR_NAND_READ_ECC 0xffd21130
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#define S10_NOC_SYS_SCR_NAND_WRITE_ECC 0xffd21134
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#define S10_NOC_SYS_SCR_OCRAM_ECC 0xffd21138
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#define S10_NOC_SYS_SCR_SDMMC_ECC 0xffd21140
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#define S10_NOC_SYS_SCR_USB0_ECC 0xffd21144
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#define S10_NOC_SYS_SCR_USB1_ECC 0xffd21148
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#define S10_NOC_SYS_SCR_CLK_MGR 0xffd2114c
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#define S10_NOC_SYS_SCR_IO_MGR 0xffd21154
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#define S10_NOC_SYS_SCR_RST_MGR 0xffd21158
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#define S10_NOC_SYS_SCR_SYS_MGR 0xffd2115c
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#define S10_NOC_SYS_SCR_OSC0_TIMER 0xffd21160
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#define S10_NOC_SYS_SCR_OSC1_TIMER 0xffd21164
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#define S10_NOC_SYS_SCR_WATCHDOG0 0xffd21168
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#define S10_NOC_SYS_SCR_WATCHDOG1 0xffd2116c
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#define S10_NOC_SYS_SCR_WATCHDOG2 0xffd21170
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#define S10_NOC_SYS_SCR_WATCHDOG3 0xffd21174
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#define S10_NOC_SYS_SCR_DAP 0xffd21178
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#define S10_NOC_SYS_SCR_L4_NOC_PROBES 0xffd21190
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#define S10_NOC_SYS_SCR_L4_NOC_QOS 0xffd21194
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#define S10_CCU_NOC_BRIDGE_CPU0_RAM 0xf7004688
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#define S10_CCU_NOC_BRIDGE_IOM_RAM 0xf7004688
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