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Workaround for Cortex A77 erratum 1508412

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Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0.
The workaround is a write sequence to several implementation defined
registers based on A77 revision.

This errata is explained in this SDEN:
https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I217993cffb3ac57c313db8490e7b8a7bb393379b
This commit is contained in:
laurenw-arm 2020-07-14 14:18:34 -05:00
parent 73740d98d9
commit aa3efe3df8
4 changed files with 88 additions and 0 deletions
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3
docs/design/cpu-specific-build-macros.rst
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@ -251,6 +251,9 @@ For Cortex-A76, the following errata build flags are defined :
For Cortex-A77, the following errata build flags are defined :
- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77
CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
- ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77
CPU. This needs to be enabled only for revision <= r1p1 of the CPU.