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plat/arm/sgi: move topology information to board folder
The platform topology description of the upcoming Arm's RD platforms have different topology than those listed in the sgi_topology.c file. So instead of adding platform specific topology into existing sgi_topology.c file, those can be added to respective board files. In order to maintain consistency with the upcoming platforms, move the existing platform topology description to respective board files. Change-Id: I4689c7d24cd0c75a3dc234370c34a85c08598abb Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
This commit is contained in:
Vijayenthiran Subramaniam
parent
9054018bd5
commit
a9fbf13e04
7 changed files with 107 additions and 62 deletions
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2018-2019, Arm Limited. All rights reserved.
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# Copyright (c) 2018-2020, Arm Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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@ -24,6 +24,7 @@ BL2_SOURCES += ${RDE1EDGE_BASE}/rde1edge_plat.c \
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BL31_SOURCES += ${SGI_CPU_SOURCES} \
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${RDE1EDGE_BASE}/rde1edge_plat.c \
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${RDE1EDGE_BASE}/rde1edge_topology.c \
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drivers/cfi/v2m/v2m_flash.c \
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lib/utils/mem_region.c \
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plat/arm/common/arm_nor_psci_mem_protect.c
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33
plat/arm/board/rde1edge/rde1edge_topology.c
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33
plat/arm/board/rde1edge/rde1edge_topology.c
Normal file
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@ -0,0 +1,33 @@
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/*
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* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat/arm/common/plat_arm.h>
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/******************************************************************************
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* The power domain tree descriptor.
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******************************************************************************/
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static const unsigned char rde1edge_pd_tree_desc[] = {
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PLAT_ARM_CLUSTER_COUNT,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_CPUS_PER_CLUSTER
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};
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/******************************************************************************
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* This function returns the topology tree information.
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******************************************************************************/
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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return rde1edge_pd_tree_desc;
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}
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/*******************************************************************************
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* The array mapping platform core position (implemented by plat_my_core_pos())
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* to the SCMI power domain ID implemented by SCP.
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******************************************************************************/
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const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
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16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
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};
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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@ -24,6 +24,7 @@ BL2_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_plat.c \
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BL31_SOURCES += ${SGI_CPU_SOURCES} \
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${RDN1EDGE_BASE}/rdn1edge_plat.c \
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${RDN1EDGE_BASE}/rdn1edge_topology.c \
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drivers/cfi/v2m/v2m_flash.c \
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lib/utils/mem_region.c \
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plat/arm/common/arm_nor_psci_mem_protect.c
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32
plat/arm/board/rdn1edge/rdn1edge_topology.c
Normal file
32
plat/arm/board/rdn1edge/rdn1edge_topology.c
Normal file
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@ -0,0 +1,32 @@
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/*
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* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat/arm/common/plat_arm.h>
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/******************************************************************************
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* The power domain tree descriptor.
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******************************************************************************/
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static const unsigned char rdn1edge_pd_tree_desc[] = {
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PLAT_ARM_CLUSTER_COUNT,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_CPUS_PER_CLUSTER
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};
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/*******************************************************************************
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* This function returns the topology tree information.
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******************************************************************************/
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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return rdn1edge_pd_tree_desc;
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}
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/*******************************************************************************
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* The array mapping platform core position (implemented by plat_my_core_pos())
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* to the SCMI power domain ID implemented by SCP.
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******************************************************************************/
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const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
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0, 1, 2, 3, 4, 5, 6, 7
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};
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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@ -24,6 +24,7 @@ BL2_SOURCES += ${SGI575_BASE}/sgi575_plat.c \
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BL31_SOURCES += ${SGI_CPU_SOURCES} \
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${SGI575_BASE}/sgi575_plat.c \
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${SGI575_BASE}/sgi575_topology.c \
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drivers/cfi/v2m/v2m_flash.c \
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lib/utils/mem_region.c \
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plat/arm/common/arm_nor_psci_mem_protect.c
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32
plat/arm/board/sgi575/sgi575_topology.c
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32
plat/arm/board/sgi575/sgi575_topology.c
Normal file
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@ -0,0 +1,32 @@
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/*
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* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat/arm/common/plat_arm.h>
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/******************************************************************************
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* The power domain tree descriptor.
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******************************************************************************/
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static const unsigned char sgi575_pd_tree_desc[] = {
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PLAT_ARM_CLUSTER_COUNT,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_CPUS_PER_CLUSTER
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};
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/*******************************************************************************
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* This function returns the topology tree information.
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******************************************************************************/
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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return sgi575_pd_tree_desc;
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}
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/*******************************************************************************
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* The array mapping platform core position (implemented by plat_my_core_pos())
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* to the SCMI power domain ID implemented by SCP.
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******************************************************************************/
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const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
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0, 1, 2, 3, 4, 5, 6, 7
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};
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@ -1,62 +1,14 @@
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/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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#include <sgi_variant.h>
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/* Topology */
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/*
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* The power domain tree descriptor. The cluster power domains are
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* arranged so that when the PSCI generic code creates the power domain tree,
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* the indices of the CPU power domain nodes it allocates match the linear
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* indices returned by plat_core_pos_by_mpidr().
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* Common topology related methods for SGI and RD based platforms
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*/
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const unsigned char sgi_pd_tree_desc[] = {
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PLAT_ARM_CLUSTER_COUNT,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_CPUS_PER_CLUSTER
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};
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/* RD-E1-Edge platform consists of 16 physical CPUS and 32 threads */
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const unsigned char rd_e1_edge_pd_tree_desc[] = {
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PLAT_ARM_CLUSTER_COUNT,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_CPUS_PER_CLUSTER,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_PE_PER_CPU
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};
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/*******************************************************************************
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* This function returns the topology tree information.
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******************************************************************************/
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM &&
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sgi_plat_info.config_id == RD_E1_EDGE_CONFIG_ID)
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return rd_e1_edge_pd_tree_desc;
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else
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return sgi_pd_tree_desc;
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}
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/*******************************************************************************
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* This function returns the core count within the cluster corresponding to
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* `mpidr`.
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@ -66,15 +18,7 @@ unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
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return CSS_SGI_MAX_CPUS_PER_CLUSTER;
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}
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/*******************************************************************************
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* The array mapping platform core position (implemented by plat_my_core_pos())
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* to the SCMI power domain ID implemented by SCP.
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******************************************************************************/
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const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[32] = {
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
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16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
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};
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#if ARM_PLAT_MT
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/******************************************************************************
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* Return the number of PE's supported by the CPU.
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*****************************************************************************/
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@ -82,3 +26,4 @@ unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr)
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{
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return CSS_SGI_MAX_PE_PER_CPU;
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}
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#endif
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