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PSCI: fix limit of 256 CPUs caused by cast to unsigned char
In psci_setup.c psci_init_pwr_domain_node() takes an unsigned char as node_idx which limits it to initialising only the first 256 CPUs. As the calling function does not check for a limit of 256 I think this is a bug so change the unsigned char to uint16_t and change the cast from the calling site in populate_power_domain_tree(). Also update the non_cpu_pwr_domain_node structure lock_index to uint16_t and update the function signature for psci_lock_init() appropriately. Finally add a define PSCI_MAX_CPUS_INDEX to psci_private.h and add a CASSERT to psci_setup.c to make sure PLATFORM_CORE_COUNT cannot exceed the index value. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Change-Id: I9e26842277db7483fd698b46bbac62aa86e71b45
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2 changed files with 19 additions and 4 deletions
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@ -42,6 +42,11 @@
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define_psci_cap(PSCI_SYSTEM_RESET2_AARCH64) | \
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define_psci_cap(PSCI_MEM_CHK_RANGE_AARCH64))
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/* Internally PSCI uses a uint16_t for various cpu indexes so
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* define a limit to number of CPUs that can be initialised.
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*/
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#define PSCI_MAX_CPUS_INDEX 0xFFFFU
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/*
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* Helper functions to get/set the fields of PSCI per-cpu data.
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*/
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@ -134,7 +139,7 @@ typedef struct non_cpu_pwr_domain_node {
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unsigned char level;
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/* For indexing the psci_lock array*/
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unsigned char lock_index;
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uint16_t lock_index;
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} non_cpu_pd_node_t;
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typedef struct cpu_pwr_domain_node {
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@ -239,7 +244,7 @@ static inline void psci_lock_release(non_cpu_pd_node_t *non_cpu_pd_node)
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#endif /* HW_ASSISTED_COHERENCY */
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static inline void psci_lock_init(non_cpu_pd_node_t *non_cpu_pd_node,
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unsigned char idx)
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uint16_t idx)
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{
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non_cpu_pd_node[idx].lock_index = idx;
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}
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@ -17,6 +17,12 @@
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#include "psci_private.h"
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/*
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* Check that PLATFORM_CORE_COUNT fits into the number of cores
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* that can be represented by PSCI_MAX_CPUS_INDEX.
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*/
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CASSERT(PLATFORM_CORE_COUNT <= (PSCI_MAX_CPUS_INDEX + 1U), assert_psci_cores_overflow);
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/*******************************************************************************
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* Per cpu non-secure contexts used to program the architectural state prior
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* return to the normal world.
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@ -34,11 +40,13 @@ unsigned int psci_caps;
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* Function which initializes the 'psci_non_cpu_pd_nodes' or the
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* 'psci_cpu_pd_nodes' corresponding to the power level.
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******************************************************************************/
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static void __init psci_init_pwr_domain_node(unsigned char node_idx,
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static void __init psci_init_pwr_domain_node(uint16_t node_idx,
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unsigned int parent_idx,
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unsigned char level)
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{
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if (level > PSCI_CPU_PWR_LVL) {
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assert(node_idx < PSCI_NUM_NON_CPU_PWR_DOMAINS);
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psci_non_cpu_pd_nodes[node_idx].level = level;
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psci_lock_init(psci_non_cpu_pd_nodes, node_idx);
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psci_non_cpu_pd_nodes[node_idx].parent_node = parent_idx;
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@ -47,6 +55,8 @@ static void __init psci_init_pwr_domain_node(unsigned char node_idx,
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} else {
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psci_cpu_data_t *svc_cpu_data;
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assert(node_idx < PLATFORM_CORE_COUNT);
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psci_cpu_pd_nodes[node_idx].parent_node = parent_idx;
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/* Initialize with an invalid mpidr */
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@ -144,7 +154,7 @@ static unsigned int __init populate_power_domain_tree(const unsigned char
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for (j = node_index;
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j < (node_index + num_children); j++)
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psci_init_pwr_domain_node((unsigned char)j,
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psci_init_pwr_domain_node((uint16_t)j,
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parent_node_index - 1U,
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(unsigned char)level);
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