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linker_script: move bss section to bl_common.ld.h

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Move the bss section to the common header. This adds BAKERY_LOCK_NORMAL
and PMF_TIMESTAMP, which previously existed only in BL31. This is not
a big deal because unused data should not be compiled in the first
place. I believe this should be controlled by BL*_SOURCES in Makefiles,
not by linker scripts.

I investigated BL1, BL2, BL2U, BL31 for plat=fvp, and BL2-AT-EL3,
BL31, BL31 for plat=uniphier. I did not see any more  unexpected
code addition.

The bss section has bigger alignment. I added BSS_ALIGN for this.

Currently, SORT_BY_ALIGNMENT() is missing in sp_min.ld.S, and with this
change, the BSS symbols in SP_MIN will be sorted by the alignment.
This is not a big deal (or, even better in terms of the image size).

Change-Id: I680ee61f84067a559bac0757f9d03e73119beb33
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada 2020-03-26 13:16:33 +09:00
parent 0a0a7a9ac8
commit a7739bc7b1
9 changed files with 27 additions and 101 deletions
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13
bl1/bl1.ld.S
View file

@ -109,18 +109,7 @@ SECTIONS
__STACKS_END__ = .;
} >RAM
/*
* The .bss section gets initialised to 0 at runtime.
* Its base address should be 16-byte aligned for better performance of the
* zero-initialization code.
*/
.bss : ALIGN(16) {
__BSS_START__ = .;
*(SORT_BY_ALIGNMENT(.bss*))
*(COMMON)
__BSS_END__ = .;
} >RAM
BSS_SECTION >RAM
XLAT_TABLE_SECTION >RAM
#if USE_COHERENT_MEM

13
bl2/bl2.ld.S
View file

@ -94,18 +94,7 @@ SECTIONS
__STACKS_END__ = .;
} >RAM
/*
* The .bss section gets initialised to 0 at runtime.
* Its base address should be 16-byte aligned for better performance of the
* zero-initialization code.
*/
.bss : ALIGN(16) {
__BSS_START__ = .;
*(SORT_BY_ALIGNMENT(.bss*))
*(COMMON)
__BSS_END__ = .;
} >RAM
BSS_SECTION >RAM
XLAT_TABLE_SECTION >RAM
#if USE_COHERENT_MEM

13
bl2/bl2_el3.ld.S
View file

@ -129,18 +129,7 @@ SECTIONS
__STACKS_END__ = .;
} >RAM
/*
* The .bss section gets initialised to 0 at runtime.
* Its base address should be 16-byte aligned for better performance of the
* zero-initialization code.
*/
.bss : ALIGN(16) {
__BSS_START__ = .;
*(SORT_BY_ALIGNMENT(.bss*))
*(COMMON)
__BSS_END__ = .;
} >RAM
BSS_SECTION >RAM
XLAT_TABLE_SECTION >RAM
#if USE_COHERENT_MEM

13
bl2u/bl2u.ld.S
View file

@ -96,18 +96,7 @@ SECTIONS
__STACKS_END__ = .;
} >RAM
/*
* The .bss section gets initialised to 0 at runtime.
* Its base address should be 16-byte aligned for better performance of the
* zero-initialization code.
*/
.bss : ALIGN(16) {
__BSS_START__ = .;
*(SORT_BY_ALIGNMENT(.bss*))
*(COMMON)
__BSS_END__ = .;
} >RAM
BSS_SECTION >RAM
XLAT_TABLE_SECTION >RAM
#if USE_COHERENT_MEM

15
bl31/bl31.ld.S
View file

@ -164,20 +164,7 @@ SECTIONS
__STACKS_END__ = .;
} >NOBITS
/*
* The .bss section gets initialised to 0 at runtime.
* Its base address should be 16-byte aligned for better performance of the
* zero-initialization code.
*/
.bss (NOLOAD) : ALIGN(16) {
__BSS_START__ = .;
*(SORT_BY_ALIGNMENT(.bss*))
*(COMMON)
BAKERY_LOCK_NORMAL
PMF_TIMESTAMP
__BSS_END__ = .;
} >NOBITS
BSS_SECTION >NOBITS
XLAT_TABLE_SECTION >NOBITS
#if USE_COHERENT_MEM

15
bl32/sp_min/sp_min.ld.S
View file

@ -107,20 +107,7 @@ SECTIONS
__STACKS_END__ = .;
} >RAM
/*
* The .bss section gets initialised to 0 at runtime.
* Its base address should be 8-byte aligned for better performance of the
* zero-initialization code.
*/
.bss (NOLOAD) : ALIGN(8) {
__BSS_START__ = .;
*(.bss*)
*(COMMON)
BAKERY_LOCK_NORMAL
PMF_TIMESTAMP
__BSS_END__ = .;
} >RAM
BSS_SECTION >RAM
XLAT_TABLE_SECTION >RAM
__BSS_SIZE__ = SIZEOF(.bss);

13
bl32/tsp/tsp.ld.S
View file

@ -97,18 +97,7 @@ SECTIONS
__STACKS_END__ = .;
} >RAM
/*
* The .bss section gets initialised to 0 at runtime.
* Its base address should be 16-byte aligned for better performance of the
* zero-initialization code.
*/
.bss : ALIGN(16) {
__BSS_START__ = .;
*(SORT_BY_ALIGNMENT(.bss*))
*(COMMON)
__BSS_END__ = .;
} >RAM
BSS_SECTION >RAM
XLAT_TABLE_SECTION >RAM
#if USE_COHERENT_MEM

18
include/common/bl_common.ld.h
View file

@ -11,8 +11,10 @@
#ifdef __aarch64__
#define STRUCT_ALIGN 8
#define BSS_ALIGN 16
#else
#define STRUCT_ALIGN 4
#define BSS_ALIGN 8
#endif
#define CPU_OPS \
@ -127,6 +129,22 @@
. = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); \
__PMF_TIMESTAMP_END__ = .;
/*
* The .bss section gets initialised to 0 at runtime.
* Its base address has bigger alignment for better performance of the
* zero-initialization code.
*/
#define BSS_SECTION \
.bss (NOLOAD) : ALIGN(BSS_ALIGN) { \
__BSS_START__ = .; \
*(SORT_BY_ALIGNMENT(.bss*)) \
*(COMMON) \
BAKERY_LOCK_NORMAL \
PMF_TIMESTAMP \
__BSS_END__ = .; \
}
/*
* The xlat_table section is for full, aligned page tables (4K).
* Removing them from .bss avoids forcing 4K alignment on

15
plat/mediatek/mt6795/bl31.ld.S
View file

@ -80,19 +80,8 @@ SECTIONS
__STACKS_END__ = .;
} >RAM
/*
* The .bss section gets initialised to 0 at runtime.
* Its base address should be 16-byte aligned for better performance of the
* zero-initialization code.
*/
.bss (NOLOAD) : ALIGN(16) {
__BSS_START__ = .;
*(.bss*)
*(COMMON)
BAKERY_LOCK_NORMAL
__BSS_END__ = .;
__RW_END__ = .;
} >RAM
BSS_SECTION >RAM
__RW_END__ = __BSS_END__;
ASSERT(. <= BL31_LIMIT, "BL3-1 image has exceeded its limit.")