fix(intel): update system counter back to 400MHz

Due to design issue, updated system counter back to hardcoded 400MHz

Change-Id: Id85b2541880fac88b2a9a0a46b27b0a0da0eed6d
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
This commit is contained in:
Sieu Mun Tang 2023-12-22 11:30:46 +08:00
parent d0e400b3c6
commit a72f86ac42
3 changed files with 64 additions and 61 deletions

View file

@ -9,14 +9,15 @@
#define PLAT_SOCFPGA_DEF_H #define PLAT_SOCFPGA_DEF_H
#include "agilex_system_manager.h" #include "agilex_system_manager.h"
#include <lib/utils_def.h>
#include <platform_def.h> #include <platform_def.h>
/* Platform Setting */ /* Platform Setting */
#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX #define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX
#define BOOT_SOURCE BOOT_SOURCE_SDMMC #define BOOT_SOURCE BOOT_SOURCE_SDMMC
#define PLAT_PRIMARY_CPU 0 #define PLAT_PRIMARY_CPU 0
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
/* FPGA config helpers */ /* FPGA config helpers */
#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
@ -64,17 +65,17 @@
#define DEVICE4_BASE (0x2000000000) #define DEVICE4_BASE (0x2000000000)
#define DEVICE4_SIZE (0x0100000000) #define DEVICE4_SIZE (0x0100000000)
#define BL2_BASE (0xffe00000) #define BL2_BASE (0xffe00000)
#define BL2_LIMIT (0xffe2b000) #define BL2_LIMIT (0xffe2b000)
#define BL31_BASE (0x1000) #define BL31_BASE (0x1000)
#define BL31_LIMIT (0x81000) #define BL31_LIMIT (0x81000)
/******************************************************************************* /*******************************************************************************
* UART related constants * UART related constants
******************************************************************************/ ******************************************************************************/
#define PLAT_UART0_BASE (0xFFC02000) #define PLAT_UART0_BASE (0xFFC02000)
#define PLAT_UART1_BASE (0xFFC02100) #define PLAT_UART1_BASE (0xFFC02100)
/******************************************************************************* /*******************************************************************************
* WDT related constants * WDT related constants
@ -84,19 +85,19 @@
/******************************************************************************* /*******************************************************************************
* GIC related constants * GIC related constants
******************************************************************************/ ******************************************************************************/
#define PLAT_GIC_BASE (0xFFFC0000) #define PLAT_GIC_BASE (0xFFFC0000)
#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
#define PLAT_GICR_BASE 0 #define PLAT_GICR_BASE 0
#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ) #define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
#define PLAT_HZ_CONVERT_TO_MHZ (1000000) #define PLAT_HZ_CONVERT_TO_MHZ (1000000)
/******************************************************************************* /*******************************************************************************
* SDMMC related pointer function * SDMMC related pointer function
******************************************************************************/ ******************************************************************************/
#define SDMMC_READ_BLOCKS mmc_read_blocks #define SDMMC_READ_BLOCKS mmc_read_blocks
#define SDMMC_WRITE_BLOCKS mmc_write_blocks #define SDMMC_WRITE_BLOCKS mmc_write_blocks
/******************************************************************************* /*******************************************************************************
* sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset
@ -105,6 +106,6 @@
#define L2_RESET_DONE_REG 0xFFD12218 #define L2_RESET_DONE_REG 0xFFD12218
/* Platform specific system counter */ /* Platform specific system counter */
#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_mpu_periph_clk() #define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400)
#endif /* PLAT_SOCFPGA_DEF_H */ #endif /* PLAT_SOCFPGA_DEF_H */

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@ -9,14 +9,15 @@
#define PLAT_SOCFPGA_DEF_H #define PLAT_SOCFPGA_DEF_H
#include <platform_def.h> #include <platform_def.h>
#include <lib/utils_def.h>
#include "n5x_system_manager.h" #include "n5x_system_manager.h"
/* Platform Setting */ /* Platform Setting */
#define PLATFORM_MODEL PLAT_SOCFPGA_N5X #define PLATFORM_MODEL PLAT_SOCFPGA_N5X
#define BOOT_SOURCE BOOT_SOURCE_SDMMC #define BOOT_SOURCE BOOT_SOURCE_SDMMC
#define PLAT_PRIMARY_CPU 0 #define PLAT_PRIMARY_CPU 0
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
/* FPGA config helpers */ /* FPGA config helpers */
#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
@ -35,10 +36,10 @@
#define SOCFPGA_RSTMGR_REG_BASE U(0xffd11000) #define SOCFPGA_RSTMGR_REG_BASE U(0xffd11000)
#define SOCFPGA_SYSMGR_REG_BASE U(0xffd12000) #define SOCFPGA_SYSMGR_REG_BASE U(0xffd12000)
#define SOCFPGA_L4_PER_SCR_REG_BASE U(0xffd21000) #define SOCFPGA_L4_PER_SCR_REG_BASE U(0xffd21000)
#define SOCFPGA_L4_SYS_SCR_REG_BASE U(0xffd21100) #define SOCFPGA_L4_SYS_SCR_REG_BASE U(0xffd21100)
#define SOCFPGA_SOC2FPGA_SCR_REG_BASE U(0xffd21200) #define SOCFPGA_SOC2FPGA_SCR_REG_BASE U(0xffd21200)
#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE U(0xffd21300) #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE U(0xffd21300)
/******************************************************************************* /*******************************************************************************
@ -65,17 +66,17 @@
#define DEVICE4_BASE (0x2000000000) #define DEVICE4_BASE (0x2000000000)
#define DEVICE4_SIZE (0x0100000000) #define DEVICE4_SIZE (0x0100000000)
#define BL2_BASE (0xffe00000) #define BL2_BASE (0xffe00000)
#define BL2_LIMIT (0xffe1b000) #define BL2_LIMIT (0xffe1b000)
#define BL31_BASE (0x1000) #define BL31_BASE (0x1000)
#define BL31_LIMIT (0x81000) #define BL31_LIMIT (0x81000)
/******************************************************************************* /*******************************************************************************
* UART related constants * UART related constants
******************************************************************************/ ******************************************************************************/
#define PLAT_UART0_BASE (0xFFC02000) #define PLAT_UART0_BASE (0xFFC02000)
#define PLAT_UART1_BASE (0xFFC02100) #define PLAT_UART1_BASE (0xFFC02100)
/******************************************************************************* /*******************************************************************************
* WDT related constants * WDT related constants
@ -85,19 +86,19 @@
/******************************************************************************* /*******************************************************************************
* GIC related constants * GIC related constants
******************************************************************************/ ******************************************************************************/
#define PLAT_GIC_BASE (0xFFFC0000) #define PLAT_GIC_BASE (0xFFFC0000)
#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
#define PLAT_GICR_BASE 0 #define PLAT_GICR_BASE 0
#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ) #define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
#define PLAT_HZ_CONVERT_TO_MHZ (1000000) #define PLAT_HZ_CONVERT_TO_MHZ (1000000)
/******************************************************************************* /*******************************************************************************
* SDMMC related pointer function * SDMMC related pointer function
******************************************************************************/ ******************************************************************************/
#define SDMMC_READ_BLOCKS mmc_read_blocks #define SDMMC_READ_BLOCKS mmc_read_blocks
#define SDMMC_WRITE_BLOCKS mmc_write_blocks #define SDMMC_WRITE_BLOCKS mmc_write_blocks
/******************************************************************************* /*******************************************************************************
* sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset
@ -106,6 +107,6 @@
#define L2_RESET_DONE_REG 0xFFD12218 #define L2_RESET_DONE_REG 0xFFD12218
/* Platform specific system counter */ /* Platform specific system counter */
#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_mpu_periph_clk() #define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400)
#endif /* PLAT_SOCFPGA_DEF_H */ #endif /* PLAT_SOCFPGA_DEF_H */

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@ -8,14 +8,15 @@
#define PLAT_SOCFPGA_DEF_H #define PLAT_SOCFPGA_DEF_H
#include <platform_def.h> #include <platform_def.h>
#include <lib/utils_def.h>
#include "s10_system_manager.h" #include "s10_system_manager.h"
/* Platform Setting */ /* Platform Setting */
#define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10 #define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10
#define BOOT_SOURCE BOOT_SOURCE_SDMMC #define BOOT_SOURCE BOOT_SOURCE_SDMMC
#define PLAT_PRIMARY_CPU 0 #define PLAT_PRIMARY_CPU 0
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
/* FPGA config helpers */ /* FPGA config helpers */
#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
@ -63,17 +64,17 @@
#define DEVICE4_BASE (0x2000000000) #define DEVICE4_BASE (0x2000000000)
#define DEVICE4_SIZE (0x0100000000) #define DEVICE4_SIZE (0x0100000000)
#define BL2_BASE (0xffe00000) #define BL2_BASE (0xffe00000)
#define BL2_LIMIT (0xffe2b000) #define BL2_LIMIT (0xffe2b000)
#define BL31_BASE (0x1000) #define BL31_BASE (0x1000)
#define BL31_LIMIT (0x81000) #define BL31_LIMIT (0x81000)
/******************************************************************************* /*******************************************************************************
* UART related constants * UART related constants
******************************************************************************/ ******************************************************************************/
#define PLAT_UART0_BASE (0xFFC02000) #define PLAT_UART0_BASE (0xFFC02000)
#define PLAT_UART1_BASE (0xFFC02100) #define PLAT_UART1_BASE (0xFFC02100)
/******************************************************************************* /*******************************************************************************
* WDT related constants * WDT related constants
@ -83,19 +84,19 @@
/******************************************************************************* /*******************************************************************************
* GIC related constants * GIC related constants
******************************************************************************/ ******************************************************************************/
#define PLAT_GIC_BASE (0xFFFC0000) #define PLAT_GIC_BASE (0xFFFC0000)
#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
#define PLAT_GICR_BASE 0 #define PLAT_GICR_BASE 0
#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ) #define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
#define PLAT_HZ_CONVERT_TO_MHZ (1000000) #define PLAT_HZ_CONVERT_TO_MHZ (1000000)
/******************************************************************************* /*******************************************************************************
* SDMMC related pointer function * SDMMC related pointer function
******************************************************************************/ ******************************************************************************/
#define SDMMC_READ_BLOCKS mmc_read_blocks #define SDMMC_READ_BLOCKS mmc_read_blocks
#define SDMMC_WRITE_BLOCKS mmc_write_blocks #define SDMMC_WRITE_BLOCKS mmc_write_blocks
/******************************************************************************* /*******************************************************************************
* sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset
@ -104,7 +105,7 @@
#define L2_RESET_DONE_REG 0xFFD12218 #define L2_RESET_DONE_REG 0xFFD12218
/* Platform specific system counter */ /* Platform specific system counter */
#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_mpu_periph_clk() #define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400)
#endif /* PLATSOCFPGA_DEF_H */ #endif /* PLATSOCFPGA_DEF_H */