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fix(intel): update system counter back to 400MHz

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Due to design issue, updated system counter back to hardcoded 400MHz

Change-Id: Id85b2541880fac88b2a9a0a46b27b0a0da0eed6d
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
This commit is contained in:
Sieu Mun Tang 2023-12-22 11:30:46 +08:00
parent d0e400b3c6
commit a72f86ac42
3 changed files with 64 additions and 61 deletions
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5
plat/intel/soc/agilex/include/socfpga_plat_def.h
View file

@ -9,6 +9,7 @@
#define PLAT_SOCFPGA_DEF_H #define PLAT_SOCFPGA_DEF_H
#include "agilex_system_manager.h" #include "agilex_system_manager.h"
#include <lib/utils_def.h>
#include <platform_def.h> #include <platform_def.h>
/* Platform Setting */ /* Platform Setting */
@ -89,7 +90,7 @@
#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
#define PLAT_GICR_BASE 0 #define PLAT_GICR_BASE 0
#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ) #define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
#define PLAT_HZ_CONVERT_TO_MHZ (1000000) #define PLAT_HZ_CONVERT_TO_MHZ (1000000)
/******************************************************************************* /*******************************************************************************
@ -105,6 +106,6 @@
#define L2_RESET_DONE_REG 0xFFD12218 #define L2_RESET_DONE_REG 0xFFD12218
/* Platform specific system counter */ /* Platform specific system counter */
#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_mpu_periph_clk() #define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400)
#endif /* PLAT_SOCFPGA_DEF_H */ #endif /* PLAT_SOCFPGA_DEF_H */

5
plat/intel/soc/n5x/include/socfpga_plat_def.h
View file

@ -9,6 +9,7 @@
#define PLAT_SOCFPGA_DEF_H #define PLAT_SOCFPGA_DEF_H
#include <platform_def.h> #include <platform_def.h>
#include <lib/utils_def.h>
#include "n5x_system_manager.h" #include "n5x_system_manager.h"
/* Platform Setting */ /* Platform Setting */
@ -90,7 +91,7 @@
#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
#define PLAT_GICR_BASE 0 #define PLAT_GICR_BASE 0
#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ) #define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
#define PLAT_HZ_CONVERT_TO_MHZ (1000000) #define PLAT_HZ_CONVERT_TO_MHZ (1000000)
/******************************************************************************* /*******************************************************************************
@ -106,6 +107,6 @@
#define L2_RESET_DONE_REG 0xFFD12218 #define L2_RESET_DONE_REG 0xFFD12218
/* Platform specific system counter */ /* Platform specific system counter */
#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_mpu_periph_clk() #define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400)
#endif /* PLAT_SOCFPGA_DEF_H */ #endif /* PLAT_SOCFPGA_DEF_H */

5
plat/intel/soc/stratix10/include/socfpga_plat_def.h
View file

@ -8,6 +8,7 @@
#define PLAT_SOCFPGA_DEF_H #define PLAT_SOCFPGA_DEF_H
#include <platform_def.h> #include <platform_def.h>
#include <lib/utils_def.h>
#include "s10_system_manager.h" #include "s10_system_manager.h"
/* Platform Setting */ /* Platform Setting */
@ -88,7 +89,7 @@
#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
#define PLAT_GICR_BASE 0 #define PLAT_GICR_BASE 0
#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ) #define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
#define PLAT_HZ_CONVERT_TO_MHZ (1000000) #define PLAT_HZ_CONVERT_TO_MHZ (1000000)
/******************************************************************************* /*******************************************************************************
@ -104,7 +105,7 @@
#define L2_RESET_DONE_REG 0xFFD12218 #define L2_RESET_DONE_REG 0xFFD12218
/* Platform specific system counter */ /* Platform specific system counter */
#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_mpu_periph_clk() #define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400)
#endif /* PLATSOCFPGA_DEF_H */ #endif /* PLATSOCFPGA_DEF_H */