From a658b46dc74ceaa51d119bd7bd9eccdefb0cc455 Mon Sep 17 00:00:00 2001
From: Kshitij Sisodia <kshitij.sisodia@arm.com>
Date: Wed, 22 Nov 2023 17:03:45 +0000
Subject: [PATCH] feat(tc): add SCMI power domain and IOMMU toggles

Compile-time controls have been added for the following:

* SCMI power domain use for DPU and GPU.
* SMMU-700: planned rework required to use IOMMU correctly
  for DPU and GPU.

These will allow easier experimentation in the future without
ad-hoc changes needed in the dts file for any sort of analysis
that requires testing different paths.

For TC3 however, the DPU is in an always on power domain so SCMI power
domains are not supported.

Co-developed-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Change-Id: If6179a3e4784c1b69f0338a8d52b552452c0eac1
---
 fdts/tc.dts                   | 14 ++++++++++++++
 fdts/tc_vers.dtsi             |  3 +++
 plat/arm/board/tc/platform.mk |  6 ++++++
 3 files changed, 23 insertions(+)

diff --git a/fdts/tc.dts b/fdts/tc.dts
index e400f2b47..d12f980e2 100644
--- a/fdts/tc.dts
+++ b/fdts/tc.dts
@@ -398,10 +398,12 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+#if TC_SCMI_PD_CTRL_EN
 		scmi_devpd: protocol@11 {
 			reg = <0x11>;
 			#power-domain-cells = <1>;
 		};
+#endif /* TC_SCMI_PD_CTRL_EN */
 
 		scmi_dvfs: protocol@13 {
 			reg = <0x13>;
@@ -550,9 +552,14 @@
 		interrupt-names = "JOB", "MMU", "GPU";
 		clocks = <&gpu_core_clk>;
 		clock-names = "shadercores";
+#if TC_SCMI_PD_CTRL_EN
 		power-domains = <&scmi_devpd GPU_SCMI_PD_IDX>;
 		scmi-perf-domain = <3>;
+#endif /* TC_SCMI_PD_CTRL_EN */
+
+#if TC_IOMMU_EN
 		iommus = <&smmu_700 0x200>;
+#endif /* TC_IOMMU_EN */
 	};
 
 	power_model_simple {
@@ -567,6 +574,7 @@
 		thermal-zone = "";
 	};
 
+#if TC_IOMMU_EN
 	smmu_700: iommu@3f000000 {
 		#iommu-cells = <1>;
 		compatible = "arm,smmu-v3";
@@ -577,6 +585,7 @@
 		interrupt-names = "eventq", "cmdq-sync", "gerror";
 		dma-coherent;
 	};
+#endif /* TC_IOMMU_EN */
 
 	dp0: display@2cc00000 {
 		#address-cells = <1>;
@@ -586,8 +595,13 @@
 		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "DPU";
 		DPU_CLK_ATTR1;
+#if TC_IOMMU_EN
 		iommus = <&smmu_700 0x100>;
+#endif /* TC_IOMMU_EN */
+#if  TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3)
 		power-domains = <&scmi_devpd DPU_SCMI_PD_IDX>;
+#endif /*  TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3) */
+
 		pl0: pipeline@0 {
 			reg = <0>;
 			DPU_CLK_ATTR2;
diff --git a/fdts/tc_vers.dtsi b/fdts/tc_vers.dtsi
index 431163242..9915685f7 100644
--- a/fdts/tc_vers.dtsi
+++ b/fdts/tc_vers.dtsi
@@ -7,8 +7,11 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
+/* If SCMI power domain control is enabled */
+#if TC_SCMI_PD_CTRL_EN
 #define GPU_SCMI_PD_IDX		(PLAT_MAX_CPUS_PER_CLUSTER + 1)
 #define DPU_SCMI_PD_IDX		(PLAT_MAX_CPUS_PER_CLUSTER + 2)
+#endif /* TC_SCMI_PD_CTRL_EN */
 
 /* All perf is normalized against the big core */
 #define BIG_CAPACITY		1024
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index dd8785980..5be1234d2 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -8,6 +8,10 @@ include common/fdt_wrappers.mk
 TARGET_FLAVOUR			:=	fvp
 # DPU with SCMI may not necessarily work, so allow its independence
 TC_DPU_USE_SCMI_CLK		:=	1
+# SCMI power domain control enable
+TC_SCMI_PD_CTRL_EN		:=	1
+# IOMMU: Enable the use of system or individual MMUs
+TC_IOMMU_EN			:=	1
 
 ifneq ($(shell expr $(TARGET_PLATFORM) \<= 1), 0)
         $(warning Platform ${PLAT}$(TARGET_PLATFORM) is deprecated. \
@@ -26,6 +30,8 @@ $(eval $(call add_defines, \
 	TARGET_PLATFORM \
 	TARGET_FLAVOUR_$(call uppercase,${TARGET_FLAVOUR}) \
 	TC_DPU_USE_SCMI_CLK \
+	TC_SCMI_PD_CTRL_EN \
+	TC_IOMMU_EN \
 ))
 
 CSS_LOAD_SCP_IMAGES	:=	1