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fix(cpus): workaround for Cortex-A78 erratum 2742426

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Cortex-A78 erratum 2742426 is a Cat B erratum that applies to
all revisions <= r1p2 and is still open.

The workaround is to set the CPUACTLR5_EL1[56:55] to 2'b01.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1401784/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I42506a87d41c9e2b30bc78c08d22f36e1f9635c1
This commit is contained in:
Bipin Ravi 2023-02-28 14:51:28 -06:00
parent 2b7150b381
commit a63332c517
4 changed files with 53 additions and 2 deletions
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4
docs/design/cpu-specific-build-macros.rst
View file

@ -317,6 +317,10 @@ For Cortex-A78, the following errata build flags are defined :
CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
it is still open.
- ``ERRATA_A78_2742426``: This applies erratum 2742426 workaround to Cortex-A78
CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and
it is still open.
- ``ERRATA_A78_2772019``: This applies errata 2772019 workaround to Cortex-A78
CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
it is still open.

2
include/lib/cpus/aarch64/cortex_a78.h
View file

@ -42,6 +42,8 @@
#define CORTEX_A78_ACTLR3_EL1 S3_0_C15_C1_2
#define CORTEX_A78_ACTLR5_EL1 S3_0_C15_C9_0
/*******************************************************************************
* CPU Activity Monitor Unit register specific definitions.
******************************************************************************/

36
lib/cpus/aarch64/cortex_a78.S
View file

@ -326,6 +326,36 @@ func check_errata_2395406
b cpu_rev_var_ls
endfunc check_errata_2395406
/* ----------------------------------------------------
* Errata Workaround for Cortex A78 Errata 2742426.
* This applies to revisions r0p0, r1p0, r1p1 and r1p2.
* It is still open.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x1, x17
* ----------------------------------------------------
*/
func errata_a78_2742426_wa
/* Check revision. */
mov x17, x30
bl check_errata_2742426
cbz x0, 1f
/* Apply the workaround */
mrs x1, CORTEX_A78_ACTLR5_EL1
bic x1, x1, #BIT(56)
orr x1, x1, #BIT(55)
msr CORTEX_A78_ACTLR5_EL1, x1
1:
ret x17
endfunc errata_a78_2742426_wa
func check_errata_2742426
/* Applies to r0p0, r1p0, r1p1, r1p2 */
mov x1, #CPU_REV(1, 2)
b cpu_rev_var_ls
endfunc check_errata_2742426
/* ----------------------------------------------------
* Errata Workaround for Cortex-A78 Errata 2772019
* This applies to revisions <= r1p2 and is still open.
@ -443,6 +473,11 @@ func cortex_a78_reset_func
bl errata_a78_2395406_wa
#endif
#if ERRATA_A78_2742426
mov x0, x18
bl errata_a78_2742426_wa
#endif
#if ERRATA_A78_2779479
mov x0, x18
bl errata_a78_2779479_wa
@ -526,6 +561,7 @@ func cortex_a78_errata_report
report_errata ERRATA_A78_2242635, cortex_a78, 2242635
report_errata ERRATA_A78_2376745, cortex_a78, 2376745
report_errata ERRATA_A78_2395406, cortex_a78, 2395406
report_errata ERRATA_A78_2742426, cortex_a78, 2742426
report_errata ERRATA_A78_2772019, cortex_a78, 2772019
report_errata ERRATA_A78_2779479, cortex_a78, 2779479
report_errata WORKAROUND_CVE_2022_23960, cortex_a78, cve_2022_23960

9
lib/cpus/cpu-ops.mk
View file

@ -357,6 +357,11 @@ ERRATA_A78_2376745 ?=0
# to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu. It is still open.
ERRATA_A78_2395406 ?=0
# Flag to apply erratum 2742426 workaround during reset. This erratum
# applies to revisions r0p0, r1p0, r1p1 and r1p2 of the A78 cpu. It is still
# open.
ERRATA_A78_2742426 ?=0
# Flag to apply erratum 2772019 workaround during powerdown. This erratum
# applies to revisions r0p0, r1p0, r1p1 and r1p2 of the A78 cpu. It is still
# open.
@ -1044,6 +1049,10 @@ $(eval $(call add_define,ERRATA_A78_2376745))
$(eval $(call assert_boolean,ERRATA_A78_2395406))
$(eval $(call add_define,ERRATA_A78_2395406))
# Process ERRATA_A78_2742426 flag
$(eval $(call assert_boolean,ERRATA_A78_2742426))
$(eval $(call add_define,ERRATA_A78_2742426))
# Process ERRATA_A78_2772019 flag
$(eval $(call assert_boolean,ERRATA_A78_2772019))
$(eval $(call add_define,ERRATA_A78_2772019))