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feat(fpmr): disable FPMR trap

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This patch enables support of FEAT_FPMR by enabling access
to FPMR register. It achieves it by setting the EnFPM bit of
SCR_EL3. This feature is currently enabled for NS world only.

Reference:
https://developer.arm.com/documentation/109697/2024_09/
Feature-descriptions/The-Armv9-5-architecture-extension?lang=en

Change-Id: I580c409b9b22f8ead0737502280fb9093a3d5dd2
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
This commit is contained in:
Arvind Ram Prakash 2024-11-11 14:32:37 -06:00
parent e372c29153
commit a57e18e433
12 changed files with 110 additions and 0 deletions
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6
docs/getting_started/build-options.rst
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@ -351,6 +351,12 @@ Common build options
This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT``
mechanism. Default value is ``0``.
- ``ENABLE_FEAT_FPMR``: Numerical value to enable support for Floating Point
Mode Register feature, allowing access to the FPMR register. FPMR register
controls the behaviors of FP8 instructions. It is an optional architectural
feature from v9.2 and upwards. This flag can take value of 0 to 2, to align
with the ``FEATURE_DETECTION`` mechanism. Default value is ``0``.
- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps)
feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained
Read Trap Register) during EL2 to EL3 context save/restore operations.