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Merge changes from topic "xlnx_fix_plat_const_preced" into integration

Browse source 
* changes:
  fix(versal2): explicitly check operators precedence
  fix(versal-net): explicitly check operators precedence
  fix(versal): explicitly check operators precedence
  fix(xilinx): explicitly check operators precedence
  fix(zynqmp): explicitly check operators precedence
  fix(versal2): add const qualifier
  fix(versal): add const qualifier
  fix(zynqmp): add const qualifier
This commit is contained in:
Joanna Farley 2024-10-29 12:11:25 +01:00 • committed by TrustedFirmware Code Review
commit a539dce9d0
17 changed files with 77 additions and 77 deletions
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2
plat/amd/versal2/bl31_setup.c
View file

@ -172,7 +172,7 @@ int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
uint32_t i;
/* Validate 'handler' and 'id' parameters */
if (handler == NULL || index >= MAX_INTR_EL3) {
if ((handler == NULL) || (index >= MAX_INTR_EL3)) {
return -EINVAL;
}

10
plat/amd/versal2/scmi.c
View file

@ -269,7 +269,7 @@ size_t plat_scmi_clock_count(unsigned int agent_id)
const char *plat_scmi_clock_get_name(unsigned int agent_id, unsigned int scmi_id)
{
struct scmi_clk *clock = clk_find(agent_id, scmi_id);
const struct scmi_clk *clock = clk_find(agent_id, scmi_id);
const char *ret;
if (clock == NULL) {
@ -287,7 +287,7 @@ int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id,
unsigned long *array, size_t *nb_elts,
uint32_t start_idx)
{
struct scmi_clk *clock = clk_find(agent_id, scmi_id);
const struct scmi_clk *clock = clk_find(agent_id, scmi_id);
if (clock == NULL) {
return SCMI_NOT_FOUND;
@ -312,7 +312,7 @@ int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id,
unsigned long plat_scmi_clock_get_rate(unsigned int agent_id, unsigned int scmi_id)
{
struct scmi_clk *clock = clk_find(agent_id, scmi_id);
const struct scmi_clk *clock = clk_find(agent_id, scmi_id);
unsigned long ret;
if ((clock == NULL)) {
@ -341,7 +341,7 @@ int32_t plat_scmi_clock_set_rate(unsigned int agent_id, unsigned int scmi_id,
int32_t plat_scmi_clock_get_state(unsigned int agent_id, unsigned int scmi_id)
{
struct scmi_clk *clock = clk_find(agent_id, scmi_id);
const struct scmi_clk *clock = clk_find(agent_id, scmi_id);
int32_t ret;
if ((clock == NULL)) {
@ -647,7 +647,7 @@ void init_scmi_server(void)
for (i = 0U; i < ARRAY_SIZE(scmi0_clock); i++) {
/* Keep i2c on 100MHz to calculate rates properly */
if (i >= CLK_I2C0_0 && i <= CLK_I2C7_0)
if ((i >= CLK_I2C0_0) && (i <= CLK_I2C7_0))
continue;
/* Keep UFS clocks to default values to get the expected rates */

2
plat/xilinx/common/ipi.c
View file

@ -70,7 +70,7 @@ static inline int is_ipi_mb_within_range(uint32_t local, uint32_t remote)
{
int ret = 1;
if (remote >= ipi_total || local >= ipi_total) {
if ((remote >= ipi_total) || (local >= ipi_total)) {
ret = 0;
}

6
plat/xilinx/common/plat_startup.c
View file

@ -237,8 +237,8 @@ enum xbl_handoff xbl_handover(entry_point_info_t *bl32,
}
target_secure = get_xbl_ss(&HandoffParams->partition[i]);
if (target_secure == XBL_FLAGS_SECURE &&
target_el == XBL_FLAGS_EL2) {
if ((target_secure == XBL_FLAGS_SECURE) &&
(target_el == XBL_FLAGS_EL2)) {
WARN("BL31: invalid security state (%i) for exception level (%i)\n",
target_secure, target_el);
continue;
@ -284,7 +284,7 @@ enum xbl_handoff xbl_handover(entry_point_info_t *bl32,
}
VERBOSE("Setting up %s entry point to:%" PRIx64 ", el:%x\n",
target_secure == XBL_FLAGS_SECURE ? "BL32" : "BL33",
(target_secure == XBL_FLAGS_SECURE) ? "BL32" : "BL33",
HandoffParams->partition[i].entry_point,
target_el);
image->pc = HandoffParams->partition[i].entry_point;

8
plat/xilinx/common/pm_service/pm_svc_main.c
View file

@ -478,9 +478,9 @@ static uintptr_t eemi_handler(uint32_t api_id, uint32_t *pm_arg,
* than other eemi calls.
*/
if (api_id == (uint32_t)PM_QUERY_DATA) {
if ((pm_arg[0] == XPM_QID_CLOCK_GET_NAME ||
pm_arg[0] == XPM_QID_PINCTRL_GET_FUNCTION_NAME) &&
ret == PM_RET_SUCCESS) {
if (((pm_arg[0] == XPM_QID_CLOCK_GET_NAME) ||
(pm_arg[0] == XPM_QID_PINCTRL_GET_FUNCTION_NAME)) &&
(ret == PM_RET_SUCCESS)) {
SMC_RET2(handle, (uint64_t)buf[0] | ((uint64_t)buf[1] << 32U),
(uint64_t)buf[2] | ((uint64_t)buf[3] << 32U));
}
@ -559,7 +559,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
uint32_t security_flag = NON_SECURE_FLAG;
uint32_t api_id;
bool status = false, status_tmp = false;
uint64_t x[4] = {x1, x2, x3, x4};
const uint64_t x[4] = {x1, x2, x3, x4};
/* Handle case where PM wasn't initialized properly */
if (pm_up == false) {

6
plat/xilinx/versal/bl31_versal_setup.c
View file

@ -76,7 +76,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
uint64_t tfa_handoff_addr;
uint32_t payload[PAYLOAD_ARG_CNT], max_size = HANDOFF_PARAMS_MAX_SIZE;
enum pm_ret_status ret_status;
uint64_t addr[HANDOFF_PARAMS_MAX_SIZE];
const uint64_t addr[HANDOFF_PARAMS_MAX_SIZE];
/*
* Do initial security configuration to allow DRAM/device access. On
@ -131,7 +131,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
enum xbl_handoff ret = xbl_handover(&bl32_image_ep_info,
&bl33_image_ep_info,
tfa_handoff_addr);
if (ret == XBL_HANDOFF_NO_STRUCT || ret == XBL_HANDOFF_INVAL_STRUCT) {
if ((ret == XBL_HANDOFF_NO_STRUCT) || (ret == XBL_HANDOFF_INVAL_STRUCT)) {
bl31_set_default_config();
} else if (ret == XBL_HANDOFF_TOO_MANY_PARTS) {
ERROR("BL31: Error too many partitions %u\n", ret);
@ -153,7 +153,7 @@ int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
uint32_t i;
/* Validate 'handler' and 'id' parameters */
if (handler == NULL || index >= MAX_INTR_EL3) {
if ((handler == NULL) || (index >= MAX_INTR_EL3)) {
return -EINVAL;
}

2
plat/xilinx/versal/plat_psci.c
View file

@ -77,7 +77,7 @@ static void versal_pwr_domain_suspend(const psci_power_state_t *target_state)
plat_versal_gic_save();
}
state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ?
state = (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) ?
PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE;
/* Send request to PMC to suspend this core */

2
plat/xilinx/versal_net/bl31_versal_net_setup.c
View file

@ -179,7 +179,7 @@ int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
uint32_t i;
/* Validate 'handler' and 'id' parameters */
if (handler == NULL || index >= MAX_INTR_EL3) {
if ((handler == NULL) || (index >= MAX_INTR_EL3)) {
return -EINVAL;
}

2
plat/xilinx/versal_net/plat_psci_pm.c
View file

@ -162,7 +162,7 @@ static void versal_net_pwr_domain_suspend(const psci_power_state_t *target_state
plat_arm_gic_save();
}
state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ?
state = (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) ?
PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE;
/* Send request to PMC to suspend this core */

10
plat/xilinx/zynqmp/aarch64/zynqmp_common.c
View file

@ -244,8 +244,8 @@ static char *zynqmp_get_silicon_idcode_name(void)
ver = chipid[1] >> ZYNQMP_EFUSE_IPDISABLE_SHIFT;
for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
if (zynqmp_devices[i].id == id &&
zynqmp_devices[i].ver == (ver & ZYNQMP_CSU_VERSION_MASK)) {
if ((zynqmp_devices[i].id == id) &&
(zynqmp_devices[i].ver == (ver & ZYNQMP_CSU_VERSION_MASK))) {
break;
}
}
@ -299,8 +299,8 @@ static char *zynqmp_print_silicon_idcode(void)
tmp = id;
tmp &= ZYNQMP_CSU_IDCODE_XILINX_ID_MASK |
ZYNQMP_CSU_IDCODE_FAMILY_MASK;
maskid = ZYNQMP_CSU_IDCODE_XILINX_ID << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT |
ZYNQMP_CSU_IDCODE_FAMILY << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT;
maskid = (ZYNQMP_CSU_IDCODE_XILINX_ID << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT) |
(ZYNQMP_CSU_IDCODE_FAMILY << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT);
if (tmp != maskid) {
ERROR("Incorrect IDCODE 0x%x, maskid 0x%x\n", id, maskid);
return "UNKN";
@ -348,7 +348,7 @@ static void zynqmp_print_platform_name(void)
{
uint32_t ver = zynqmp_get_silicon_ver();
uint32_t rtl = zynqmp_get_rtl_ver();
char *label = "Unknown";
const char *label = "Unknown";
switch (ver) {
case ZYNQMP_CSU_VERSION_QEMU:

2
plat/xilinx/zynqmp/plat_psci.c
View file

@ -105,7 +105,7 @@ static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state)
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ?
state = (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) ?
PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE;
/* Send request to PMU to suspend this core */

38
plat/xilinx/zynqmp/pm_service/pm_api_clock.c
View file

@ -1226,7 +1226,7 @@ static struct pm_clock clocks[] = {
.control_reg = CRF_APB_ACPU_CTRL,
.status_reg = 0,
.parents = &((int32_t []) {
CLK_ACPU | PARENT_CLK_NODE2 << CLK_PARENTS_ID_LEN,
(CLK_ACPU | (PARENT_CLK_NODE2 << CLK_PARENTS_ID_LEN)),
CLK_NA_PARENT
}),
.nodes = &acpu_full_nodes,
@ -2117,7 +2117,7 @@ static struct pm_clock clocks[] = {
.control_reg = CRF_APB_ACPU_CTRL,
.status_reg = 0,
.parents = &((int32_t []) {
CLK_ACPU | PARENT_CLK_NODE2 << CLK_PARENTS_ID_LEN,
(CLK_ACPU | (PARENT_CLK_NODE2 << CLK_PARENTS_ID_LEN)),
CLK_NA_PARENT
}),
.nodes = &acpu_half_nodes,
@ -2140,7 +2140,7 @@ static struct pm_clock clocks[] = {
.control_reg = CRF_APB_GPU_REF_CTRL,
.status_reg = 0,
.parents = &((int32_t []) {
CLK_GPU_REF | PARENT_CLK_NODE2 << CLK_PARENTS_ID_LEN,
(CLK_GPU_REF | (PARENT_CLK_NODE2 << CLK_PARENTS_ID_LEN)),
CLK_NA_PARENT
}),
.nodes = &gpu_pp0_nodes,
@ -2151,7 +2151,7 @@ static struct pm_clock clocks[] = {
.control_reg = CRF_APB_GPU_REF_CTRL,
.status_reg = 0,
.parents = &((int32_t []) {
CLK_GPU_REF | PARENT_CLK_NODE2 << CLK_PARENTS_ID_LEN,
(CLK_GPU_REF | (PARENT_CLK_NODE2 << CLK_PARENTS_ID_LEN)),
CLK_NA_PARENT
}),
.nodes = &gpu_pp1_nodes,
@ -2176,7 +2176,7 @@ static struct pm_clock clocks[] = {
.control_reg = CRL_APB_CPU_R5_CTRL,
.status_reg = 0,
.parents = &((int32_t []) {
CLK_CPU_R5 | PARENT_CLK_NODE2 << CLK_PARENTS_ID_LEN,
(CLK_CPU_R5 | (PARENT_CLK_NODE2 << CLK_PARENTS_ID_LEN)),
CLK_DUMMY_PARENT,
CLK_NA_PARENT
}),
@ -2456,8 +2456,8 @@ enum pm_ret_status pm_api_clock_get_num_clocks(uint32_t *nclocks)
void pm_api_clock_get_name(uint32_t clock_id, char *name)
{
if (clock_id == CLK_MAX) {
memcpy(name, END_OF_CLK, sizeof(END_OF_CLK) > CLK_NAME_LEN ?
CLK_NAME_LEN : sizeof(END_OF_CLK));
memcpy(name, END_OF_CLK, ((sizeof(END_OF_CLK) > CLK_NAME_LEN) ?
CLK_NAME_LEN : sizeof(END_OF_CLK)));
} else if ((clock_id > CLK_MAX) || (!pm_clock_valid(clock_id))) {
memset(name, 0, CLK_NAME_LEN);
} else if (clock_id < CLK_MAX_OUTPUT_CLK) {
@ -2486,7 +2486,7 @@ enum pm_ret_status pm_api_clock_get_topology(uint32_t clock_id,
uint32_t index,
uint32_t *topology)
{
struct pm_clock_node *clock_nodes;
const struct pm_clock_node *clock_nodes;
uint8_t num_nodes;
uint32_t i;
uint16_t typeflags;
@ -2543,7 +2543,7 @@ enum pm_ret_status pm_api_clock_get_fixedfactor_params(uint32_t clock_id,
uint32_t *mul,
uint32_t *div)
{
struct pm_clock_node *clock_nodes;
const struct pm_clock_node *clock_nodes;
uint8_t num_nodes;
uint32_t type, i;
@ -2598,7 +2598,7 @@ enum pm_ret_status pm_api_clock_get_parents(uint32_t clock_id,
uint32_t *parents)
{
uint32_t i;
int32_t *clk_parents;
const int32_t *clk_parents;
if (!pm_clock_valid(clock_id)) {
return PM_RET_ERROR_ARGS;
@ -2675,7 +2675,7 @@ enum pm_ret_status pm_api_clock_get_max_divisor(enum clock_id clock_id,
uint32_t *max_div)
{
uint32_t i;
struct pm_clock_node *nodes;
const struct pm_clock_node *nodes;
if (clock_id >= CLK_MAX_OUTPUT_CLK) {
return PM_RET_ERROR_ARGS;
@ -2789,7 +2789,7 @@ struct pm_pll *pm_clock_get_pll(enum clock_id clock_id)
enum pm_ret_status pm_clock_get_pll_node_id(enum clock_id clock_id,
enum pm_node_id *node_id)
{
struct pm_pll *pll = pm_clock_get_pll(clock_id);
const struct pm_pll *pll = pm_clock_get_pll(clock_id);
if (pll != NULL) {
*node_id = pll->nid;
@ -2812,10 +2812,10 @@ struct pm_pll *pm_clock_get_pll_by_related_clk(enum clock_id clock_id)
uint32_t i;
for (i = 0; i < ARRAY_SIZE(pm_plls); i++) {
if (pm_plls[i].pre_src == clock_id ||
pm_plls[i].post_src == clock_id ||
pm_plls[i].div2 == clock_id ||
pm_plls[i].bypass == clock_id) {
if ((pm_plls[i].pre_src == clock_id) ||
(pm_plls[i].post_src == clock_id) ||
(pm_plls[i].div2 == clock_id) ||
(pm_plls[i].bypass == clock_id)) {
return &pm_plls[i];
}
}
@ -2990,7 +2990,7 @@ enum pm_ret_status pm_clock_set_pll_mode(enum clock_id clock_id,
{
struct pm_pll *pll = pm_clock_get_pll(clock_id);
if ((pll == NULL) || (mode != PLL_FRAC_MODE && mode != PLL_INT_MODE)) {
if ((pll == NULL) || ((mode != PLL_FRAC_MODE) && (mode != PLL_INT_MODE))) {
return PM_RET_ERROR_ARGS;
}
pll->mode = mode;
@ -3011,7 +3011,7 @@ enum pm_ret_status pm_clock_set_pll_mode(enum clock_id clock_id,
enum pm_ret_status pm_clock_get_pll_mode(enum clock_id clock_id,
uint32_t *mode)
{
struct pm_pll *pll = pm_clock_get_pll(clock_id);
const struct pm_pll *pll = pm_clock_get_pll(clock_id);
if ((pll == NULL) || (mode == NULL)) {
return PM_RET_ERROR_ARGS;
@ -3052,7 +3052,7 @@ enum pm_ret_status pm_clock_id_is_valid(uint32_t clock_id)
uint8_t pm_clock_has_div(uint32_t clock_id, enum pm_clock_div_id div_id)
{
uint32_t i;
struct pm_clock_node *nodes;
const struct pm_clock_node *nodes;
if (clock_id >= CLK_MAX_OUTPUT_CLK) {
return 0;

8
plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
View file

@ -165,8 +165,8 @@ static enum pm_ret_status pm_ioctl_config_tcm_comb(uint32_t value)
static enum pm_ret_status pm_ioctl_set_tapdelay_bypass(uint32_t type,
uint32_t value)
{
if ((value != PM_TAPDELAY_BYPASS_ENABLE &&
value != PM_TAPDELAY_BYPASS_DISABLE) || type >= PM_TAPDELAY_MAX) {
if ((((value != PM_TAPDELAY_BYPASS_ENABLE) &&
(value != PM_TAPDELAY_BYPASS_DISABLE)) || (type >= PM_TAPDELAY_MAX))) {
return PM_RET_ERROR_ARGS;
}
@ -481,7 +481,7 @@ static enum pm_ret_status pm_ioctl_afi(uint32_t index,
uint32_t value)
{
uint32_t mask;
uint32_t regarr[] = {0xFD360000U,
const uint32_t regarr[] = {0xFD360000U,
0xFD360014U,
0xFD370000U,
0xFD370014U,
@ -682,7 +682,7 @@ enum pm_ret_status pm_api_ioctl(enum pm_node_id nid,
*/
enum pm_ret_status tfa_ioctl_bitmask(uint32_t *bit_mask)
{
uint8_t supported_ids[] = {
const uint8_t supported_ids[] = {
IOCTL_GET_RPU_OPER_MODE,
IOCTL_SET_RPU_OPER_MODE,
IOCTL_RPU_BOOT_ADDR_CONFIG,

2
plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
View file

@ -2088,7 +2088,7 @@ enum pm_ret_status pm_api_pinctrl_get_pin_groups(uint32_t pin,
uint16_t *groups)
{
uint32_t i;
uint16_t *grps;
const uint16_t *grps;
if (pin >= MAX_PIN) {
return PM_RET_ERROR_ARGS;

2
plat/xilinx/zynqmp/pm_service/pm_client.c
View file

@ -218,7 +218,7 @@ static void pm_client_set_wakeup_sources(void)
node = irq_to_pm_node(irq);
reg &= ~lowest_set;
if (node > NODE_UNKNOWN && node < NODE_MAX) {
if ((node > NODE_UNKNOWN) && (node < NODE_MAX)) {
if (pm_wakeup_nodes_set[node] == 0U) {
ret = pm_set_wakeup_source(NODE_APU, node, 1U);
pm_wakeup_nodes_set[node] = (ret == PM_RET_SUCCESS) ? 1U : 0U;

8
plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
View file

@ -1657,7 +1657,7 @@ enum pm_ret_status pm_pll_set_parameter(enum pm_node_id nid,
uint32_t payload[PAYLOAD_ARG_CNT];
/* Check if given node ID is a PLL node */
if (nid < NODE_APLL || nid > NODE_IOPLL) {
if ((nid < NODE_APLL) || (nid > NODE_IOPLL)) {
return PM_RET_ERROR_ARGS;
}
@ -1688,7 +1688,7 @@ enum pm_ret_status pm_pll_get_parameter(enum pm_node_id nid,
uint32_t payload[PAYLOAD_ARG_CNT];
/* Check if given node ID is a PLL node */
if (nid < NODE_APLL || nid > NODE_IOPLL) {
if ((nid < NODE_APLL) || (nid > NODE_IOPLL)) {
return PM_RET_ERROR_ARGS;
}
@ -1721,7 +1721,7 @@ enum pm_ret_status pm_pll_set_mode(enum pm_node_id nid, enum pm_pll_mode mode)
uint32_t payload[PAYLOAD_ARG_CNT];
/* Check if given node ID is a PLL node */
if (nid < NODE_APLL || nid > NODE_IOPLL) {
if ((nid < NODE_APLL) || (nid > NODE_IOPLL)) {
return PM_RET_ERROR_ARGS;
}
@ -1749,7 +1749,7 @@ enum pm_ret_status pm_pll_get_mode(enum pm_node_id nid, enum pm_pll_mode *mode)
uint32_t payload[PAYLOAD_ARG_CNT];
/* Check if given node ID is a PLL node */
if (nid < NODE_APLL || nid > NODE_IOPLL) {
if ((nid < NODE_APLL) || (nid > NODE_IOPLL)) {
return PM_RET_ERROR_ARGS;
}

44
plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
View file

@ -374,7 +374,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
uint32_t value = 0U;
ret = pm_fpga_get_status(&value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32)));
}
case PM_SECURE_RSA_AES:
@ -389,15 +389,15 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
}
SMC_RET2(handle,
(uint64_t)result[0] | ((uint64_t)result[1] << 32),
(uint64_t)result[2] | ((uint64_t)result[3] << 32));
((uint64_t)result[0] | ((uint64_t)result[1] << 32)),
((uint64_t)result[2] | ((uint64_t)result[3] << 32)));
case PM_IOCTL:
{
uint32_t value = 0U;
ret = pm_ioctl(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3], &value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32)));
}
case PM_QUERY_DATA:
@ -406,8 +406,8 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
pm_query_data(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3], data);
SMC_RET2(handle, (uint64_t)data[0] | ((uint64_t)data[1] << 32),
(uint64_t)data[2] | ((uint64_t)data[3] << 32));
SMC_RET2(handle, ((uint64_t)data[0] | ((uint64_t)data[1] << 32)),
((uint64_t)data[2] | ((uint64_t)data[3] << 32)));
}
case PM_CLOCK_ENABLE:
@ -423,7 +423,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
uint32_t value = 0U;
ret = pm_clock_getstate(pm_arg[0], &value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32)));
}
case PM_CLOCK_SETDIVIDER:
@ -435,7 +435,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
uint32_t value = 0U;
ret = pm_clock_getdivider(pm_arg[0], &value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32)));
}
case PM_CLOCK_SETPARENT:
@ -447,7 +447,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
uint32_t value = 0U;
ret = pm_clock_getparent(pm_arg[0], &value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32U)));
}
case PM_GET_TRUSTZONE_VERSION:
@ -472,7 +472,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
{
ret = pm_secure_image(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3], &result[0]);
SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32U),
SMC_RET2(handle, ((uint64_t)ret | ((uint64_t)result[0] << 32U)),
result[1]);
}
@ -482,7 +482,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
ret = pm_fpga_read(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3],
&value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32U)));
}
case PM_SECURE_AES:
@ -490,7 +490,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
uint32_t value = 0U;
ret = pm_aes_engine(pm_arg[0], pm_arg[1], &value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32U)));
}
case PM_PLL_SET_PARAMETER:
@ -502,7 +502,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
uint32_t value = 0U;
ret = pm_pll_get_parameter(pm_arg[0], pm_arg[1], &value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value << 32U));
SMC_RET1(handle, ((uint64_t)ret | ((uint64_t)value << 32U)));
}
case PM_PLL_SET_MODE:
@ -514,7 +514,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
uint32_t mode = 0U;
ret = pm_pll_get_mode(pm_arg[0], &mode);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)mode << 32U));
SMC_RET1(handle, ((uint64_t)ret | ((uint64_t)mode << 32U)));
}
case PM_REGISTER_ACCESS:
@ -523,7 +523,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
ret = pm_register_access(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3], &value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32U)));
}
case PM_EFUSE_ACCESS:
@ -538,7 +538,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
}
#endif
ret = pm_efuse_access(pm_arg[0], pm_arg[1], &value);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
SMC_RET1(handle, (uint64_t)ret | (((uint64_t)value) << 32U));
}
case PM_FPGA_GET_VERSION:
@ -549,8 +549,8 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
PM_PACK_PAYLOAD5(payload, smc_fid & FUNCID_NUM_MASK,
pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]);
ret = pm_ipi_send_sync(primary_proc, payload, ret_payload, 3U);
SMC_RET2(handle, (uint64_t)ret | (uint64_t)ret_payload[0] << 32U,
(uint64_t)ret_payload[1] | (uint64_t)ret_payload[2] << 32U);
SMC_RET2(handle, ((uint64_t)ret | ((uint64_t)ret_payload[0] << 32U)),
((uint64_t)ret_payload[1] | ((uint64_t)ret_payload[2] << 32U)));
}
case PM_FEATURE_CHECK:
@ -560,8 +560,8 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
ret = pm_feature_check(pm_arg[0], &version, bit_mask,
ARRAY_SIZE(bit_mask));
SMC_RET2(handle, (uint64_t)ret | ((uint64_t)version << 32U),
(uint64_t)bit_mask[0] | ((uint64_t)bit_mask[1] << 32U));
SMC_RET2(handle, ((uint64_t)ret | ((uint64_t)version << 32U)),
((uint64_t)bit_mask[0] | ((uint64_t)bit_mask[1] << 32U)));
}
default:
@ -570,7 +570,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
pm_arg[2], pm_arg[3], pm_arg[4]);
ret = pm_ipi_send_sync(primary_proc, payload, result,
RET_PAYLOAD_ARG_CNT);
SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32U),
(uint64_t)result[1] | ((uint64_t)result[2] << 32U));
SMC_RET2(handle, ((uint64_t)ret | ((uint64_t)result[0] << 32U)),
((uint64_t)result[1] | ((uint64_t)result[2] << 32U)));
}
}