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Introduce preliminary support for Neoverse Zeus

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Change-Id: If56d1e200a31bd716726d7fdc1cc0ae8a63ba3ee
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
This commit is contained in:
John Tsichritzis 2018-10-08 17:09:43 +01:00
parent 620d9832f9
commit a4546e80f5
3 changed files with 86 additions and 1 deletions
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23
include/lib/cpus/aarch64/neoverse_zeus.h Normal file
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@ -0,0 +1,23 @@
/*
* Copyright (c) 2019, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef NEOVERSE_ZEUS_H
#define NEOVERSE_ZEUS_H
#define NEOVERSE_ZEUS_MIDR U(0x410FD400)
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
#define NEOVERSE_ZEUS_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
#define NEOVERSE_ZEUS_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define NEOVERSE_ZEUS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#endif /* NEOVERSE_ZEUS_H */

60
lib/cpus/aarch64/neoverse_zeus.S Normal file
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@ -0,0 +1,60 @@
/*
* Copyright (c) 2019, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <common/bl_common.h>
#include <neoverse_zeus.h>
#include <cpu_macros.S>
#include <plat_macros.S>
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
*/
func neoverse_zeus_core_pwr_dwn
/* ---------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
mrs x0, NEOVERSE_ZEUS_CPUPWRCTLR_EL1
orr x0, x0, #NEOVERSE_ZEUS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr NEOVERSE_ZEUS_CPUPWRCTLR_EL1, x0
isb
ret
endfunc neoverse_zeus_core_pwr_dwn
/*
* Errata printing function for Neoverse Zeus. Must follow AAPCS.
*/
#if REPORT_ERRATA
func neoverse_zeus_errata_report
ret
endfunc neoverse_zeus_errata_report
#endif
/* ---------------------------------------------
* This function provides Neoverse-Zeus specific
* register information for crash reporting.
* It needs to return with x6 pointing to
* a list of register names in ascii and
* x8 - x15 having values of registers to be
* reported.
* ---------------------------------------------
*/
.section .rodata.neoverse_zeus_regs, "aS"
neoverse_zeus_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
func neoverse_zeus_cpu_reg_dump
adr x6, neoverse_zeus_regs
mrs x8, NEOVERSE_ZEUS_CPUECTLR_EL1
ret
endfunc neoverse_zeus_cpu_reg_dump
declare_cpu_ops neoverse_zeus, NEOVERSE_ZEUS_MIDR, \
CPU_NO_RESET_FUNC, \
neoverse_zeus_core_pwr_dwn

4
plat/arm/board/fvp/platform.mk
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@ -104,7 +104,9 @@ FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
lib/cpus/aarch64/cortex_a75.S \
lib/cpus/aarch64/cortex_a76.S \
lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/cortex_deimos.S
lib/cpus/aarch64/cortex_deimos.S \
lib/cpus/aarch64/neoverse_zeus.S
else
FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S
endif