From a29cb3c0854e38ef8f389abb88ec42bfb4d8dd54 Mon Sep 17 00:00:00 2001 From: Jayanth Dodderi Chidanand Date: Tue, 11 Apr 2023 21:58:21 +0100 Subject: [PATCH] refactor(cpus): convert the Cortex-A510 to use cpu helpers Change-Id: I6d26092525c2d5255a741515071ee7ed873aa52d Signed-off-by: Jayanth Dodderi Chidanand --- include/lib/cpus/aarch64/cortex_a510.h | 20 ++++++++-- lib/cpus/aarch64/cortex_a510.S | 54 ++++++++------------------ 2 files changed, 33 insertions(+), 41 deletions(-) diff --git a/include/lib/cpus/aarch64/cortex_a510.h b/include/lib/cpus/aarch64/cortex_a510.h index 6af85a863..337aac3ef 100644 --- a/include/lib/cpus/aarch64/cortex_a510.h +++ b/include/lib/cpus/aarch64/cortex_a510.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, ARM Limited. All rights reserved. + * Copyright (c) 2022-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,11 +14,13 @@ ******************************************************************************/ #define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4 #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT U(19) +#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH U(1) #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1) #define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT U(23) #define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT U(46) #define CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR U(2) -#define CORTEX_A510_CPUECTLR_EL1_ATOM U(38) +#define CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT U(38) +#define CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH U(3) /******************************************************************************* * CPU Power Control register specific definitions @@ -30,6 +32,12 @@ * Complex auxiliary control register specific definitions ******************************************************************************/ #define CORTEX_A510_CMPXACTLR_EL1 S3_0_C15_C1_3 +#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1) +#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(25) +#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1) +#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE U(3) +#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT U(10) +#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH U(2) /******************************************************************************* * Auxiliary control register specific definitions @@ -37,5 +45,11 @@ #define CORTEX_A510_CPUACTLR_EL1 S3_0_C15_C1_0 #define CORTEX_A510_CPUACTLR_EL1_BIT_17 (ULL(1) << 17) #define CORTEX_A510_CPUACTLR_EL1_BIT_38 (ULL(1) << 38) +#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1) +#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(18) +#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1) +#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE U(1) +#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT U(18) +#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH U(1) -#endif /* CORTEX_A510_H */ \ No newline at end of file +#endif /* CORTEX_A510_H */ diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S index 58ced603f..6fce24e02 100644 --- a/lib/cpus/aarch64/cortex_a510.S +++ b/lib/cpus/aarch64/cortex_a510.S @@ -23,10 +23,8 @@ workaround_reset_start cortex_a510, ERRATUM(1922240), ERRATA_A510_1922240 /* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */ - mrs x0, CORTEX_A510_CMPXACTLR_EL1 - mov x1, #3 - bfi x0, x1, #10, #2 - msr CORTEX_A510_CMPXACTLR_EL1, x0 + sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE, \ + CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH workaround_reset_end cortex_a510, ERRATUM(1922240) check_erratum_ls cortex_a510, ERRATUM(1922240), CPU_REV(0, 0) @@ -53,10 +51,8 @@ check_erratum_range cortex_a510, ERRATUM(2041909), CPU_REV(0, 2), CPU_REV(0, 2) workaround_reset_start cortex_a510, ERRATUM(2042739), ERRATA_A510_2042739 /* Apply the workaround by disabling ReadPreferUnique. */ - mrs x0, CORTEX_A510_CPUECTLR_EL1 - mov x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE - bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, #1 - msr CORTEX_A510_CPUECTLR_EL1, x0 + sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE, \ + CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH workaround_reset_end cortex_a510, ERRATUM(2042739) check_erratum_ls cortex_a510, ERRATUM(2042739), CPU_REV(0, 2) @@ -76,18 +72,14 @@ workaround_reset_end cortex_a510, ERRATUM(2172148) check_erratum_ls cortex_a510, ERRATUM(2172148), CPU_REV(1, 0) workaround_reset_start cortex_a510, ERRATUM(2218950), ERRATA_A510_2218950 - /* Source register for BFI */ - mov x1, #1 - /* Set bit 18 in CPUACTLR_EL1 */ - mrs x0, CORTEX_A510_CPUACTLR_EL1 - bfi x0, x1, #18, #1 - msr CORTEX_A510_CPUACTLR_EL1, x0 + sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \ + CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH /* Set bit 25 in CMPXACTLR_EL1 */ - mrs x0, CORTEX_A510_CMPXACTLR_EL1 - bfi x0, x1, #25, #1 - msr CORTEX_A510_CMPXACTLR_EL1, x0 + sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \ + CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH + workaround_reset_end cortex_a510, ERRATUM(2218950) check_erratum_ls cortex_a510, ERRATUM(2218950), CPU_REV(1, 0) @@ -117,10 +109,8 @@ check_erratum_ls cortex_a510, ERRATUM(2250311), CPU_REV(1, 0) workaround_reset_start cortex_a510, ERRATUM(2288014), ERRATA_A510_2288014 /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */ - mrs x0, CORTEX_A510_CPUACTLR_EL1 - mov x1, #1 - bfi x0, x1, #18, #1 - msr CORTEX_A510_CPUACTLR_EL1, x0 + sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE, \ + CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH workaround_reset_end cortex_a510, ERRATUM(2288014) check_erratum_ls cortex_a510, ERRATUM(2288014), CPU_REV(1, 0) @@ -131,9 +121,7 @@ workaround_reset_start cortex_a510, ERRATUM(2347730), ERRATA_A510_2347730 * specific microarchitectural clock gating * behaviour. */ - mrs x1, CORTEX_A510_CPUACTLR_EL1 - orr x1, x1, CORTEX_A510_CPUACTLR_EL1_BIT_17 - msr CORTEX_A510_CPUACTLR_EL1, x1 + sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_17 workaround_reset_end cortex_a510, ERRATUM(2347730) check_erratum_ls cortex_a510, ERRATUM(2347730), CPU_REV(1, 1) @@ -145,22 +133,14 @@ workaround_reset_start cortex_a510, ERRATUM(2371937), ERRATA_A510_2371937 * IMP_CPUECTLR_EL1.ATOM=0b010. ATOM is found * in [40:38] of CPUECTLR_EL1. */ - mrs x0, CORTEX_A510_CPUECTLR_EL1 - mov x1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR - bfi x0, x1, CORTEX_A510_CPUECTLR_EL1_ATOM, #3 - msr CORTEX_A510_CPUECTLR_EL1, x0 + sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR, \ + CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT, CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH workaround_reset_end cortex_a510, ERRATUM(2371937) check_erratum_ls cortex_a510, ERRATUM(2371937), CPU_REV(1, 1) workaround_reset_start cortex_a510, ERRATUM(2666669), ERRATA_A510_2666669 - /* - * Workaround will set IMP_CPUACTLR_EL1[38] - * to 0b1. - */ - mrs x1, CORTEX_A510_CPUACTLR_EL1 - orr x1, x1, CORTEX_A510_CPUACTLR_EL1_BIT_38 - msr CORTEX_A510_CPUACTLR_EL1, x1 + sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_38 workaround_reset_end cortex_a510, ERRATUM(2666669) check_erratum_ls cortex_a510, ERRATUM(2666669), CPU_REV(1, 1) @@ -195,9 +175,7 @@ func cortex_a510_core_pwr_dwn * Enable CPU power down bit in power control register * --------------------------------------------------- */ - mrs x0, CORTEX_A510_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_A510_CPUPWRCTLR_EL1, x0 + sysreg_bit_set CORTEX_A510_CPUPWRCTLR_EL1, CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT isb ret endfunc cortex_a510_core_pwr_dwn