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refactor(fvp_ve): fdts: prepare Cortex-A5 and A7 model DTs
The DT files for the Cortex-A5 and Cortex-A7 FVP models include the shared rtsm_ve-motherboard.dtsi file, which we need to sync with the upstream Linux version soon. To prepare for its changed structure there, adjust the top-level #address-cells and #size-cells properties to be compatible with the expectations of the Linux version. Also extend the interrupt map to cover all peripherals listed in the motherboard file, and use the proper GIC macros to make them more readable on the way. Change-Id: I7d1493f1a200e8350530f912833f9ffcc5f94b21 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Andre Przywara
parent
6b2721c016
commit
a25349b75c
2 changed files with 65 additions and 37 deletions
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@ -1,16 +1,18 @@
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/*
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* Copyright (c) 2019-2020, Arm Limited. All rights reserved.
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* Copyright (c) 2019-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/dts-v1/;
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/ {
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model = "V2P-CA5s";
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compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#address-cells = <2>;
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#size-cells = <1>;
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cpus {
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@ -27,12 +29,12 @@
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x1000000>;
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reg = <0 0x80000000 0x1000000>;
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};
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hdlcd@2a110000 {
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compatible = "arm,hdlcd";
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reg = <0x2a110000 0x1000>;
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reg = <0 0x2a110000 0x1000>;
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interrupts = <0 85 4>;
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clocks = <&oscclk3>;
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clock-names = "pxlclk";
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@ -40,12 +42,12 @@
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scu@2c000000 {
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compatible = "arm,cortex-a5-scu";
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reg = <0x2c000000 0x58>;
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reg = <0 0x2c000000 0x58>;
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};
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watchdog@2c000620 {
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compatible = "arm,cortex-a5-twd-wdt";
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reg = <0x2c000620 0x20>;
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reg = <0 0x2c000620 0x20>;
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interrupts = <1 14 0x304>;
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};
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@ -54,8 +56,8 @@
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x2c001000 0x1000>,
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<0x2c000100 0x100>;
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reg = <0 0x2c001000 0x1000>,
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<0 0x2c000100 0x100>;
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};
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dcc {
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@ -122,22 +124,34 @@
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x08000000 0x04000000>,
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<1 0 0x14000000 0x04000000>,
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<2 0 0x18000000 0x04000000>,
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<3 0 0x1c000000 0x04000000>,
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<4 0 0x0c000000 0x04000000>,
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<5 0 0x10000000 0x04000000>;
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ranges = <0 0 0 0x08000000 0x04000000>,
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<1 0 0 0x14000000 0x04000000>,
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<2 0 0 0x18000000 0x04000000>,
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<3 0 0 0x1c000000 0x04000000>,
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<4 0 0 0x0c000000 0x04000000>,
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<5 0 0 0x10000000 0x04000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 63>;
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interrupt-map = <0 0 0 &gic 0 0 4>,
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<0 0 1 &gic 0 1 4>,
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<0 0 2 &gic 0 2 4>,
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<0 0 3 &gic 0 3 4>,
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<0 0 4 &gic 0 4 4>,
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<0 0 5 &gic 0 5 4>,
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<0 0 42 &gic 0 42 4>;
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interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 43 &gic GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 44 &gic GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 46 &gic GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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#include "rtsm_ve-motherboard-aarch32.dtsi"
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};
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@ -1,9 +1,11 @@
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/*
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* Copyright (c) 2019-2020, Arm Limited. All rights reserved.
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* Copyright (c) 2019-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/dts-v1/;
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/ {
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@ -11,22 +13,22 @@
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compatible = "arm,vexpress,v2f-1xv7", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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#size-cells = <1>;
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cpus {
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#address-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0 0>;
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reg = <0>;
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};
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};
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memory@0,80000000 {
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device_type = "memory";
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reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
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reg = <0 0x80000000 0x80000000>; /* 2GB @ 2GB */
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};
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gic: interrupt-controller@2c001000 {
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@ -34,10 +36,10 @@
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0x2c001000 0 0x1000>,
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<0 0x2c002000 0 0x1000>,
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<0 0x2c004000 0 0x2000>,
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<0 0x2c006000 0 0x2000>;
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reg = <0 0x2c001000 0x1000>,
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<0 0x2c002000 0x1000>,
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<0 0x2c004000 0x2000>,
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<0 0x2c006000 0x2000>;
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interrupts = <1 9 0xf04>;
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};
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@ -63,13 +65,25 @@
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 63>;
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interrupt-map = <0 0 0 &gic 0 0 4>,
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<0 0 1 &gic 0 1 4>,
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<0 0 2 &gic 0 2 4>,
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<0 0 3 &gic 0 3 4>,
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<0 0 4 &gic 0 4 4>,
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<0 0 5 &gic 0 5 4>,
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<0 0 42 &gic 0 42 4>;
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interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 43 &gic GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 44 &gic GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 46 &gic GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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#include "rtsm_ve-motherboard-aarch32.dtsi"
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};
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