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refactor(sgi): replace build-option prefix to "NRD"

Browse source 
As of now, CSS_SGI_PLATFORM_VARIANT and CSS_SGI_CHIP_COUNT are the
external build option that "sgi" platforms support. As "sgi" has been
renamed to "neoverse_rd" and the source files have been migrated out of
the css directory, replace the prefix "CSS_SGI" with "NRD".

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I27989ff42404d823dd2a8cd22ff485497ccb62d4
This commit is contained in:
Rohit Mathew 2024-02-03 19:06:16 +00:00 • committed by Omkar Anand Kulkarni
parent 4ced59568e
commit a1e6467b0e
22 changed files with 145 additions and 142 deletions
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27
docs/plat/arm/arm-build-options.rst
View file

@ -121,17 +121,6 @@ Arm CSS Platform-Specific Build Options
management operations and for SCP RAM Firmware transfer. If this option
is set to 1, then SCMI/SDS drivers will be used. Default is 0.
- ``CSS_SGI_CHIP_COUNT``: Configures the number of chips on a SGI/RD platform
which supports multi-chip operation. If ``CSS_SGI_CHIP_COUNT`` is set to any
valid value greater than 1, the platform code performs required configuration
to support multi-chip operation.
- ``CSS_SGI_PLATFORM_VARIANT``: Selects the variant of a SGI/RD platform. A
particular SGI/RD platform may have multiple variants which may differ in
core count, cluster count or other peripherals. This build option is used
to select the appropriate platform variant for the build. The range of
valid values is platform specific.
- ``CSS_SYSTEM_GRACEFUL_RESET``: Build option to enable graceful powerdown of
CPU core on reset. This build option can be used on CSS platforms that
require all the CPUs to execute the CPU specific power down sequence to
@ -152,8 +141,22 @@ Arm Juno Build Options
AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
images.
Arm Neoverse RD Platform Build Options
--------------------------------------
- ``NRD_CHIP_COUNT``: Configures the number of chips on a Neoverse RD platform
which supports multi-chip operation. If ``NRD_CHIP_COUNT`` is set to any
valid value greater than 1, the platform code performs required configuration
to support multi-chip operation.
- ``NRD_PLATFORM_VARIANT``: Selects the variant of a Neoverse RD platform. A
particular Neoverse RD platform may have multiple variants which may differ in
core count, cluster count or other peripherals. This build option is used to
select the appropriate platform variant for the build. The range of valid
values is platform specific.
--------------
.. |FIP in a GPT image| image:: ../../resources/diagrams/FIP_in_a_GPT_image.png
*Copyright (c) 2019-2023, Arm Limited. All rights reserved.*
*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*

20
plat/arm/board/neoverse_rd/common/include/nrd_base_platform_def.h
View file

@ -14,7 +14,7 @@
#include <plat/arm/css/common/css_def.h>
#include <plat/common/common_def.h>
#define PLATFORM_CORE_COUNT (CSS_SGI_CHIP_COUNT * \
#define PLATFORM_CORE_COUNT (NRD_CHIP_COUNT * \
PLAT_ARM_CLUSTER_COUNT * \
CSS_SGI_MAX_CPUS_PER_CLUSTER * \
CSS_SGI_MAX_PE_PER_CPU)
@ -34,19 +34,19 @@
*/
#if defined(IMAGE_BL31)
# if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)
# define PLAT_ARM_MMAP_ENTRIES (10 + ((CSS_SGI_CHIP_COUNT - 1) * 3))
# define MAX_XLAT_TABLES (8 + ((CSS_SGI_CHIP_COUNT - 1) * 3))
# define PLAT_ARM_MMAP_ENTRIES (10 + ((NRD_CHIP_COUNT - 1) * 3))
# define MAX_XLAT_TABLES (8 + ((NRD_CHIP_COUNT - 1) * 3))
# define PLAT_SP_IMAGE_MMAP_REGIONS 12
# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 14
# else
# define PLAT_ARM_MMAP_ENTRIES (5 + ((CSS_SGI_CHIP_COUNT - 1) * 3))
# define MAX_XLAT_TABLES (6 + ((CSS_SGI_CHIP_COUNT - 1) * 3))
# define PLAT_ARM_MMAP_ENTRIES (5 + ((NRD_CHIP_COUNT - 1) * 3))
# define MAX_XLAT_TABLES (6 + ((NRD_CHIP_COUNT - 1) * 3))
# endif
#elif defined(IMAGE_BL32)
# define PLAT_ARM_MMAP_ENTRIES 8
# define MAX_XLAT_TABLES 5
#elif defined(IMAGE_BL2)
# define PLAT_ARM_MMAP_ENTRIES (11 + (CSS_SGI_CHIP_COUNT - 1))
# define PLAT_ARM_MMAP_ENTRIES (11 + (NRD_CHIP_COUNT - 1))
/*
* MAX_XLAT_TABLES entries need to be doubled because when the address width
@ -55,7 +55,7 @@
* > 40 bits
*
*/
# define MAX_XLAT_TABLES (7 + ((CSS_SGI_CHIP_COUNT - 1) * 2))
# define MAX_XLAT_TABLES (7 + ((NRD_CHIP_COUNT - 1) * 2))
#elif !USE_ROMLIB
# define PLAT_ARM_MMAP_ENTRIES 11
# define MAX_XLAT_TABLES 7
@ -90,10 +90,10 @@
*
*/
#if TRUSTED_BOARD_BOOT
# define PLAT_ARM_MAX_BL2_SIZE (0x20000 + ((CSS_SGI_CHIP_COUNT - 1) * \
# define PLAT_ARM_MAX_BL2_SIZE (0x20000 + ((NRD_CHIP_COUNT - 1) * \
0x2000))
#else
# define PLAT_ARM_MAX_BL2_SIZE (0x14000 + ((CSS_SGI_CHIP_COUNT - 1) * \
# define PLAT_ARM_MAX_BL2_SIZE (0x14000 + ((NRD_CHIP_COUNT - 1) * \
0x2000))
#endif
@ -269,7 +269,7 @@
#define SBSA_SECURE_WDOG_TIMEOUT UL(100)
/* Number of SCMI channels on the platform */
#define PLAT_ARM_SCMI_CHANNEL_COUNT CSS_SGI_CHIP_COUNT
#define PLAT_ARM_SCMI_CHANNEL_COUNT NRD_CHIP_COUNT
/*
* Mapping definition of the TrustZone Controller for ARM SGI/RD platforms

8
plat/arm/board/neoverse_rd/common/nrd-common.mk
View file

@ -16,9 +16,9 @@ EL3_EXCEPTION_HANDLING := 0
HANDLE_EA_EL3_FIRST_NS := 0
CSS_SGI_CHIP_COUNT := 1
NRD_CHIP_COUNT := 1
CSS_SGI_PLATFORM_VARIANT := 0
NRD_PLATFORM_VARIANT := 0
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0
@ -58,9 +58,9 @@ ifneq (${RESET_TO_BL31},0)
Please set RESET_TO_BL31 to 0.")
endif
$(eval $(call add_define,CSS_SGI_CHIP_COUNT))
$(eval $(call add_define,NRD_CHIP_COUNT))
$(eval $(call add_define,CSS_SGI_PLATFORM_VARIANT))
$(eval $(call add_define,NRD_PLATFORM_VARIANT))
override CSS_LOAD_SCP_IMAGES := 0
override NEED_BL2U := no

6
plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
View file

@ -38,7 +38,7 @@ static scmi_channel_plat_info_t plat_rd_scmi_info[] = {
.db_modify_mask = 0x1,
.ring_doorbell = &mhuv2_ring_doorbell,
},
#if (CSS_SGI_CHIP_COUNT > 1)
#if (NRD_CHIP_COUNT > 1)
{
.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1),
@ -49,7 +49,7 @@ static scmi_channel_plat_info_t plat_rd_scmi_info[] = {
.ring_doorbell = &mhuv2_ring_doorbell,
},
#endif
#if (CSS_SGI_CHIP_COUNT > 2)
#if (NRD_CHIP_COUNT > 2)
{
.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2),
@ -60,7 +60,7 @@ static scmi_channel_plat_info_t plat_rd_scmi_info[] = {
.ring_doorbell = &mhuv2_ring_doorbell,
},
#endif
#if (CSS_SGI_CHIP_COUNT > 3)
#if (NRD_CHIP_COUNT > 3)
{
.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3),

6
plat/arm/board/neoverse_rd/common/nrd_plat.c
View file

@ -52,13 +52,13 @@ const mmap_region_t plat_arm_mmap[] = {
CSS_SGI_MAP_DEVICE,
SOC_CSS_MAP_DEVICE,
ARM_MAP_NS_DRAM1,
#if CSS_SGI_CHIP_COUNT > 1
#if NRD_CHIP_COUNT > 1
CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1),
#endif
#if CSS_SGI_CHIP_COUNT > 2
#if NRD_CHIP_COUNT > 2
CSS_SGI_MAP_DEVICE_REMOTE_CHIP(2),
#endif
#if CSS_SGI_CHIP_COUNT > 3
#if NRD_CHIP_COUNT > 3
CSS_SGI_MAP_DEVICE_REMOTE_CHIP(3),
#endif
#if ARM_BL31_IN_DRAM

6
plat/arm/board/neoverse_rd/common/nrd_plat_v2.c
View file

@ -44,13 +44,13 @@ const mmap_region_t plat_arm_mmap[] = {
SOC_PLATFORM_PERIPH_MAP_DEVICE,
SOC_SYSTEM_PERIPH_MAP_DEVICE,
ARM_MAP_NS_DRAM1,
#if CSS_SGI_CHIP_COUNT > 1
#if NRD_CHIP_COUNT > 1
SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(1),
#endif
#if CSS_SGI_CHIP_COUNT > 2
#if NRD_CHIP_COUNT > 2
SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(2),
#endif
#if CSS_SGI_CHIP_COUNT > 3
#if NRD_CHIP_COUNT > 3
SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(3),
#endif
#if ARM_BL31_IN_DRAM

4
plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
View file

@ -38,9 +38,9 @@
*/
#ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
CSS_SGI_CHIP_COUNT)
NRD_CHIP_COUNT)
#define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
CSS_SGI_CHIP_COUNT)
NRD_CHIP_COUNT)
#else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)

10
plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk
View file

@ -62,14 +62,14 @@ NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
$(eval $(call CREATE_SEQ,SEQ,2))
ifneq ($(CSS_SGI_CHIP_COUNT),$(filter $(CSS_SGI_CHIP_COUNT),$(SEQ)))
ifneq ($(NRD_CHIP_COUNT),$(filter $(NRD_CHIP_COUNT),$(SEQ)))
$(error "Chip count for RDN1Edge platform should be one of $(SEQ), currently \
set to ${CSS_SGI_CHIP_COUNT}.")
set to ${NRD_CHIP_COUNT}.")
endif
ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
$(error "CSS_SGI_PLATFORM_VARIANT for RD-N1-Edge should always be 0, \
currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
ifneq ($(NRD_PLATFORM_VARIANT),0)
$(error "NRD_PLATFORM_VARIANT for RD-N1-Edge should always be 0, \
currently set to ${NRD_PLATFORM_VARIANT}.")
endif
override CTX_INCLUDE_AARCH32_REGS := 0

8
plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c
View file

@ -22,7 +22,7 @@ static const mmap_region_t rdn1edge_dynamic_mmap[] = {
static struct gic600_multichip_data rdn1e1_multichip_data __init = {
.rt_owner_base = PLAT_ARM_GICD_BASE,
.rt_owner = 0,
.chip_count = CSS_SGI_CHIP_COUNT,
.chip_count = NRD_CHIP_COUNT,
.chip_addrs = {
PLAT_ARM_GICD_BASE >> 16,
(PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16
@ -70,12 +70,12 @@ void bl31_platform_setup(void)
unsigned int i;
int ret;
if (plat_arm_sgi_get_multi_chip_mode() == 0 && CSS_SGI_CHIP_COUNT > 1) {
if (plat_arm_sgi_get_multi_chip_mode() == 0 && NRD_CHIP_COUNT > 1) {
ERROR("Chip Count is set to %d but multi-chip mode not enabled\n",
CSS_SGI_CHIP_COUNT);
NRD_CHIP_COUNT);
panic();
} else if (plat_arm_sgi_get_multi_chip_mode() == 1 &&
CSS_SGI_CHIP_COUNT > 1) {
NRD_CHIP_COUNT > 1) {
INFO("Enabling support for multi-chip in RD-N1-Edge\n");
for (i = 0; i < ARRAY_SIZE(rdn1edge_dynamic_mmap); i++) {

6
plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_topology.c
View file

@ -11,10 +11,10 @@
* The power domain tree descriptor.
******************************************************************************/
static const unsigned char rdn1edge_pd_tree_desc[] = {
(PLAT_ARM_CLUSTER_COUNT) * (CSS_SGI_CHIP_COUNT),
(PLAT_ARM_CLUSTER_COUNT) * (NRD_CHIP_COUNT),
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
#if (CSS_SGI_CHIP_COUNT > 1)
#if (NRD_CHIP_COUNT > 1)
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER
#endif
@ -41,7 +41,7 @@ const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
#if (CSS_SGI_CHIP_COUNT > 1)
#if (NRD_CHIP_COUNT > 1)
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x0)),
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x1)),
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x2)),

18
plat/arm/board/neoverse_rd/platform/rdn2/include/platform_def.h
View file

@ -11,9 +11,9 @@
#include <nrd_sdei.h>
#include <nrd_soc_platform_def_v2.h>
#if (CSS_SGI_PLATFORM_VARIANT == 1)
#if (NRD_PLATFORM_VARIANT == 1)
#define PLAT_ARM_CLUSTER_COUNT U(8)
#elif (CSS_SGI_PLATFORM_VARIANT == 2)
#elif (NRD_PLATFORM_VARIANT == 2)
#define PLAT_ARM_CLUSTER_COUNT U(4)
#else
#define PLAT_ARM_CLUSTER_COUNT U(16)
@ -34,9 +34,9 @@
#define TZC400_OFFSET UL(0x1000000)
#if (CSS_SGI_PLATFORM_VARIANT == 1)
#if (NRD_PLATFORM_VARIANT == 1)
#define TZC400_COUNT U(2)
#elif (CSS_SGI_PLATFORM_VARIANT == 2)
#elif (NRD_PLATFORM_VARIANT == 2)
#define TZC400_COUNT U(4)
#else
#define TZC400_COUNT U(8)
@ -68,16 +68,16 @@
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
#ifdef __aarch64__
#if (CSS_SGI_PLATFORM_VARIANT == 2)
#if (NRD_PLATFORM_VARIANT == 2)
#define CSS_SGI_ADDR_BITS_PER_CHIP U(46) /* 64TB */
#else
#define CSS_SGI_ADDR_BITS_PER_CHIP U(42) /* 4TB */
#endif
#define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
CSS_SGI_CHIP_COUNT)
NRD_CHIP_COUNT)
#define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
CSS_SGI_CHIP_COUNT)
NRD_CHIP_COUNT)
#else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
@ -90,9 +90,9 @@
/* Virtual address used by dynamic mem_protect for chunk_base */
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000)
#if (CSS_SGI_PLATFORM_VARIANT == 1)
#if (NRD_PLATFORM_VARIANT == 1)
#define PLAT_ARM_GICR_BASE UL(0x30100000)
#elif (CSS_SGI_PLATFORM_VARIANT == 3)
#elif (NRD_PLATFORM_VARIANT == 3)
#define PLAT_ARM_GICR_BASE UL(0x30300000)
#else
#define PLAT_ARM_GICR_BASE UL(0x301C0000)

16
plat/arm/board/neoverse_rd/platform/rdn2/platform.mk
View file

@ -4,16 +4,16 @@
#
RD_N2_VARIANTS := 0 1 2 3
ifneq ($(CSS_SGI_PLATFORM_VARIANT),\
$(filter $(CSS_SGI_PLATFORM_VARIANT),$(RD_N2_VARIANTS)))
$(error "CSS_SGI_PLATFORM_VARIANT for RD-N2 should be 0, 1, 2 or 3, currently \
set to ${CSS_SGI_PLATFORM_VARIANT}.")
ifneq ($(NRD_PLATFORM_VARIANT),\
$(filter $(NRD_PLATFORM_VARIANT),$(RD_N2_VARIANTS)))
$(error "NRD_PLATFORM_VARIANT for RD-N2 should be 0, 1, 2 or 3, currently \
set to ${NRD_PLATFORM_VARIANT}.")
endif
$(eval $(call CREATE_SEQ,SEQ,4))
ifneq ($(CSS_SGI_CHIP_COUNT),$(filter $(CSS_SGI_CHIP_COUNT),$(SEQ)))
ifneq ($(NRD_CHIP_COUNT),$(filter $(NRD_CHIP_COUNT),$(SEQ)))
$(error "Chip count for RD-N2-MC should be either $(SEQ) \
currently it is set to ${CSS_SGI_CHIP_COUNT}.")
currently it is set to ${NRD_CHIP_COUNT}.")
endif
# RD-N2 platform uses GIC-700 which is based on GICv4.1
@ -21,7 +21,7 @@ GIC_ENABLE_V4_EXTN := 1
GIC_EXT_INTID := 1
#Enable GIC Multichip Extension only for Multichip Platforms
ifeq (${CSS_SGI_PLATFORM_VARIANT}, 2)
ifeq (${NRD_PLATFORM_VARIANT}, 2)
GICV3_IMPL_GIC600_MULTICHIP := 1
endif
@ -62,7 +62,7 @@ BL1_SOURCES += ${RDN2_BASE}/rdn2_trusted_boot.c
BL2_SOURCES += ${RDN2_BASE}/rdn2_trusted_boot.c
endif
ifeq (${CSS_SGI_PLATFORM_VARIANT}, 2)
ifeq (${NRD_PLATFORM_VARIANT}, 2)
BL31_SOURCES += drivers/arm/gic/v3/gic600_multichip.c
# Enable dynamic addition of MMAP regions in BL31

38
plat/arm/board/neoverse_rd/platform/rdn2/rdn2_plat.c
View file

@ -15,68 +15,68 @@
#include <rdn2_ras.h>
#if defined(IMAGE_BL31)
#if (CSS_SGI_PLATFORM_VARIANT == 2)
#if (NRD_PLATFORM_VARIANT == 2)
static const mmap_region_t rdn2mc_dynamic_mmap[] = {
#if CSS_SGI_CHIP_COUNT > 1
#if NRD_CHIP_COUNT > 1
ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1),
#endif
#if CSS_SGI_CHIP_COUNT > 2
#if NRD_CHIP_COUNT > 2
ARM_MAP_SHARED_RAM_REMOTE_CHIP(2),
CSS_SGI_MAP_DEVICE_REMOTE_CHIP(2),
#endif
#if CSS_SGI_CHIP_COUNT > 3
#if NRD_CHIP_COUNT > 3
ARM_MAP_SHARED_RAM_REMOTE_CHIP(3),
CSS_SGI_MAP_DEVICE_REMOTE_CHIP(3),
#endif
};
#endif
#if (CSS_SGI_PLATFORM_VARIANT == 2)
#if (NRD_PLATFORM_VARIANT == 2)
static struct gic600_multichip_data rdn2mc_multichip_data __init = {
.rt_owner_base = PLAT_ARM_GICD_BASE,
.rt_owner = 0,
.chip_count = CSS_SGI_CHIP_COUNT,
.chip_count = NRD_CHIP_COUNT,
.chip_addrs = {
PLAT_ARM_GICD_BASE >> 16,
#if CSS_SGI_CHIP_COUNT > 1
#if NRD_CHIP_COUNT > 1
(PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
#endif
#if CSS_SGI_CHIP_COUNT > 2
#if NRD_CHIP_COUNT > 2
(PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
#endif
#if CSS_SGI_CHIP_COUNT > 3
#if NRD_CHIP_COUNT > 3
(PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
#endif
},
.spi_ids = {
{PLAT_ARM_GICD_BASE, 32, 511},
#if CSS_SGI_CHIP_COUNT > 1
#if NRD_CHIP_COUNT > 1
{PLAT_ARM_GICD_BASE, 512, 991},
#endif
#if CSS_SGI_CHIP_COUNT > 2
#if NRD_CHIP_COUNT > 2
{PLAT_ARM_GICD_BASE, 4096, 4575},
#endif
#if CSS_SGI_CHIP_COUNT > 3
#if NRD_CHIP_COUNT > 3
{PLAT_ARM_GICD_BASE, 4576, 5055},
#endif
}
};
#endif
#if (CSS_SGI_PLATFORM_VARIANT == 2)
#if (NRD_PLATFORM_VARIANT == 2)
static uintptr_t rdn2mc_multichip_gicr_frames[] = {
/* Chip 0's GICR Base */
PLAT_ARM_GICR_BASE,
#if CSS_SGI_CHIP_COUNT > 1
#if NRD_CHIP_COUNT > 1
/* Chip 1's GICR BASE */
PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1),
#endif
#if CSS_SGI_CHIP_COUNT > 2
#if NRD_CHIP_COUNT > 2
/* Chip 2's GICR BASE */
PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2),
#endif
#if CSS_SGI_CHIP_COUNT > 3
#if NRD_CHIP_COUNT > 3
/* Chip 3's GICR BASE */
PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3),
#endif
@ -106,13 +106,13 @@ unsigned int plat_arm_sgi_get_multi_chip_mode(void)
#if defined(IMAGE_BL31)
void bl31_platform_setup(void)
{
#if (CSS_SGI_PLATFORM_VARIANT == 2)
#if (NRD_PLATFORM_VARIANT == 2)
int ret;
unsigned int i;
if (plat_arm_sgi_get_multi_chip_mode() == 0) {
ERROR("Chip Count is set to %u but multi-chip mode is not "
"enabled\n", CSS_SGI_CHIP_COUNT);
ERROR("Chip Count is %u but multi-chip mode is not enabled\n",
NRD_CHIP_COUNT);
panic();
} else {
INFO("Enabling multi-chip support for RD-N2 variant\n");

14
plat/arm/board/neoverse_rd/platform/rdn2/rdn2_security.c
View file

@ -21,21 +21,21 @@ static const arm_tzc_regions_info_t tzc_regions[] = {
{}
};
#if (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 1)
static const arm_tzc_regions_info_t tzc_regions_mc[][CSS_SGI_CHIP_COUNT - 1] = {
#if (NRD_PLATFORM_VARIANT == 2 && NRD_CHIP_COUNT > 1)
static const arm_tzc_regions_info_t tzc_regions_mc[][NRD_CHIP_COUNT - 1] = {
{
/* TZC memory regions for second chip */
SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(1),
{}
},
#if CSS_SGI_CHIP_COUNT > 2
#if NRD_CHIP_COUNT > 2
{
/* TZC memory regions for third chip */
SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(2),
{}
},
#endif
#if CSS_SGI_CHIP_COUNT > 3
#if NRD_CHIP_COUNT > 3
{
/* TZC memory regions for fourth chip */
SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(3),
@ -43,7 +43,7 @@ static const arm_tzc_regions_info_t tzc_regions_mc[][CSS_SGI_CHIP_COUNT - 1] = {
},
#endif
};
#endif /* CSS_SGI_PLATFORM_VARIANT && CSS_SGI_CHIP_COUNT */
#endif /* NRD_PLATFORM_VARIANT && NRD_CHIP_COUNT */
/* Initialize the secure environment */
void plat_arm_security_setup(void)
@ -56,10 +56,10 @@ void plat_arm_security_setup(void)
arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
}
#if (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 1)
#if (NRD_PLATFORM_VARIANT == 2 && NRD_CHIP_COUNT > 1)
unsigned int j;
for (i = 1; i < CSS_SGI_CHIP_COUNT; i++) {
for (i = 1; i < NRD_CHIP_COUNT; i++) {
INFO("Configuring TrustZone Controller for Chip %u\n", i);
for (j = 0; j < TZC400_COUNT; j++) {

16
plat/arm/board/neoverse_rd/platform/rdn2/rdn2_topology.c
View file

@ -11,27 +11,27 @@
* The power domain tree descriptor.
******************************************************************************/
const unsigned char rd_n2_pd_tree_desc[] = {
(PLAT_ARM_CLUSTER_COUNT) * (CSS_SGI_CHIP_COUNT),
(PLAT_ARM_CLUSTER_COUNT) * (NRD_CHIP_COUNT),
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
#if (PLAT_ARM_CLUSTER_COUNT > 4 || \
(CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 1))
(NRD_PLATFORM_VARIANT == 2 && NRD_CHIP_COUNT > 1))
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
#endif
#if (PLAT_ARM_CLUSTER_COUNT > 8 || \
(CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 2))
(NRD_PLATFORM_VARIANT == 2 && NRD_CHIP_COUNT > 2))
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
#endif
#if (PLAT_ARM_CLUSTER_COUNT > 8 || \
(CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 3))
(NRD_PLATFORM_VARIANT == 2 && NRD_CHIP_COUNT > 3))
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
@ -51,25 +51,25 @@ const unsigned char *plat_get_power_domain_tree_desc(void)
* The array mapping platform core position (implemented by plat_my_core_pos())
* to the SCMI power domain ID implemented by SCP.
******************************************************************************/
#if (CSS_SGI_PLATFORM_VARIANT == 2)
#if (NRD_PLATFORM_VARIANT == 2)
const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
#if (CSS_SGI_CHIP_COUNT > 1)
#if (NRD_CHIP_COUNT > 1)
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x0)),
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x1)),
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x2)),
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x3)),
#endif
#if (CSS_SGI_CHIP_COUNT > 2)
#if (NRD_CHIP_COUNT > 2)
(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x0)),
(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x1)),
(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x2)),
(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x3)),
#endif
#if (CSS_SGI_CHIP_COUNT > 3)
#if (NRD_CHIP_COUNT > 3)
(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x0)),
(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x1)),
(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x2)),

6
plat/arm/board/neoverse_rd/platform/rdv1/platform.mk
View file

@ -59,9 +59,9 @@ $(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
override CTX_INCLUDE_AARCH32_REGS := 0
override ENABLE_FEAT_AMU := 1
ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
$(error "CSS_SGI_PLATFORM_VARIANT for RD-V1 should always be 0, \
currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
ifneq ($(NRD_PLATFORM_VARIANT),0)
$(error "NRD_PLATFORM_VARIANT for RD-V1 should always be 0, \
currently set to ${NRD_PLATFORM_VARIANT}.")
endif
# Enable the flag since RD-V1 has a system level cache

4
plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
View file

@ -51,9 +51,9 @@
/* Physical and virtual address space limits for MMU in AARCH64 mode */
#define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
CSS_SGI_CHIP_COUNT)
NRD_CHIP_COUNT)
#define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
CSS_SGI_CHIP_COUNT)
NRD_CHIP_COUNT)
/* GIC related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)

10
plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk
View file

@ -56,9 +56,9 @@ $(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
$(eval $(call CREATE_SEQ,SEQ,4))
ifneq ($(CSS_SGI_CHIP_COUNT),$(filter $(CSS_SGI_CHIP_COUNT),$(SEQ)))
ifneq ($(NRD_CHIP_COUNT),$(filter $(NRD_CHIP_COUNT),$(SEQ)))
$(error "Chip count for RD-V1-MC should be either $(SEQ) \
currently it is set to ${CSS_SGI_CHIP_COUNT}.")
currently it is set to ${NRD_CHIP_COUNT}.")
endif
FDT_SOURCES += ${RDV1MC_BASE}/fdts/${PLAT}_nt_fw_config.dts
@ -70,9 +70,9 @@ $(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
override CTX_INCLUDE_AARCH32_REGS := 0
override ENABLE_FEAT_AMU := 1
ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
$(error "CSS_SGI_PLATFORM_VARIANT for RD-V1-MC should always be 0, \
currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
ifneq ($(NRD_PLATFORM_VARIANT),0)
$(error "NRD_PLATFORM_VARIANT for RD-V1-MC should always be 0, \
currently set to ${NRD_PLATFORM_VARIANT}.")
endif
# Enable the flag since RD-V1-MC has a system level cache

26
plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c
View file

@ -17,12 +17,12 @@ static const mmap_region_t rdv1mc_dynamic_mmap[] = {
ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1),
SOC_CSS_MAP_DEVICE_REMOTE_CHIP(1),
#if (CSS_SGI_CHIP_COUNT > 2)
#if (NRD_CHIP_COUNT > 2)
ARM_MAP_SHARED_RAM_REMOTE_CHIP(2),
CSS_SGI_MAP_DEVICE_REMOTE_CHIP(2),
SOC_CSS_MAP_DEVICE_REMOTE_CHIP(2),
#endif
#if (CSS_SGI_CHIP_COUNT > 3)
#if (NRD_CHIP_COUNT > 3)
ARM_MAP_SHARED_RAM_REMOTE_CHIP(3),
CSS_SGI_MAP_DEVICE_REMOTE_CHIP(3),
SOC_CSS_MAP_DEVICE_REMOTE_CHIP(3)
@ -32,14 +32,14 @@ static const mmap_region_t rdv1mc_dynamic_mmap[] = {
static struct gic600_multichip_data rdv1mc_multichip_data __init = {
.rt_owner_base = PLAT_ARM_GICD_BASE,
.rt_owner = 0,
.chip_count = CSS_SGI_CHIP_COUNT,
.chip_count = NRD_CHIP_COUNT,
.chip_addrs = {
PLAT_ARM_GICD_BASE >> 16,
(PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
#if (CSS_SGI_CHIP_COUNT > 2)
#if (NRD_CHIP_COUNT > 2)
(PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
#endif
#if (CSS_SGI_CHIP_COUNT > 3)
#if (NRD_CHIP_COUNT > 3)
(PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
#endif
},
@ -47,10 +47,10 @@ static struct gic600_multichip_data rdv1mc_multichip_data __init = {
{PLAT_ARM_GICD_BASE, RDV1MC_CHIP0_SPI_START,
RDV1MC_CHIP0_SPI_END},
{0, 0, 0},
#if (CSS_SGI_CHIP_COUNT > 2)
#if (NRD_CHIP_COUNT > 2)
{0, 0, 0},
#endif
#if (CSS_SGI_CHIP_COUNT > 3)
#if (NRD_CHIP_COUNT > 3)
{0, 0, 0},
#endif
}
@ -61,11 +61,11 @@ static uintptr_t rdv1mc_multichip_gicr_frames[] = {
PLAT_ARM_GICR_BASE,
/* Chip 1's GICR BASE */
PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1),
#if (CSS_SGI_CHIP_COUNT > 2)
#if (NRD_CHIP_COUNT > 2)
/* Chip 2's GICR BASE */
PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2),
#endif
#if (CSS_SGI_CHIP_COUNT > 3)
#if (NRD_CHIP_COUNT > 3)
/* Chip 3's GICR BASE */
PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3),
#endif
@ -102,12 +102,12 @@ void bl31_platform_setup(void)
unsigned int i;
if ((plat_arm_sgi_get_multi_chip_mode() == 0) &&
(CSS_SGI_CHIP_COUNT > 1)) {
ERROR("Chip Count is set to %u but multi-chip mode is not "
"enabled\n", CSS_SGI_CHIP_COUNT);
(NRD_CHIP_COUNT > 1)) {
ERROR("Chip Count is %u but multi-chip mode is not enabled\n",
NRD_CHIP_COUNT);
panic();
} else if ((plat_arm_sgi_get_multi_chip_mode() == 1) &&
(CSS_SGI_CHIP_COUNT > 1)) {
(NRD_CHIP_COUNT > 1)) {
INFO("Enabling support for multi-chip in RD-V1-MC\n");
for (i = 0; i < ARRAY_SIZE(rdv1mc_dynamic_mmap); i++) {

14
plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c
View file

@ -14,21 +14,21 @@ static const arm_tzc_regions_info_t tzc_regions[] = {
{}
};
#if CSS_SGI_CHIP_COUNT > 1
static const arm_tzc_regions_info_t tzc_regions_mc[][CSS_SGI_CHIP_COUNT - 1] = {
#if NRD_CHIP_COUNT > 1
static const arm_tzc_regions_info_t tzc_regions_mc[][NRD_CHIP_COUNT - 1] = {
{
/* TZC memory regions for second chip */
SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(1),
{}
},
#if CSS_SGI_CHIP_COUNT > 2
#if NRD_CHIP_COUNT > 2
{
/* TZC memory regions for third chip */
SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(2),
{}
},
#endif
#if CSS_SGI_CHIP_COUNT > 3
#if NRD_CHIP_COUNT > 3
{
/* TZC memory regions for fourth chip */
SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(3),
@ -36,7 +36,7 @@ static const arm_tzc_regions_info_t tzc_regions_mc[][CSS_SGI_CHIP_COUNT - 1] = {
},
#endif
};
#endif /* CSS_SGI_CHIP_COUNT */
#endif /* NRD_CHIP_COUNT */
/* Initialize the secure environment */
void plat_arm_security_setup(void)
@ -49,10 +49,10 @@ void plat_arm_security_setup(void)
arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
}
#if CSS_SGI_CHIP_COUNT > 1
#if NRD_CHIP_COUNT > 1
unsigned int j;
for (i = 1; i < CSS_SGI_CHIP_COUNT; i++) {
for (i = 1; i < NRD_CHIP_COUNT; i++) {
INFO("Configuring TrustZone Controller for Chip %u\n", i);
for (j = 0; j < TZC400_COUNT; j++) {

14
plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_topology.c
View file

@ -14,24 +14,24 @@
* The power domain tree descriptor.
******************************************************************************/
const unsigned char rd_v1_mc_pd_tree_desc_multi_chip[] = {
((PLAT_ARM_CLUSTER_COUNT) * (CSS_SGI_CHIP_COUNT)),
((PLAT_ARM_CLUSTER_COUNT) * (NRD_CHIP_COUNT)),
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
#if (CSS_SGI_CHIP_COUNT > 1)
#if (NRD_CHIP_COUNT > 1)
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
#endif
#if (CSS_SGI_CHIP_COUNT > 2)
#if (NRD_CHIP_COUNT > 2)
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
#endif
#if (CSS_SGI_CHIP_COUNT > 3)
#if (NRD_CHIP_COUNT > 3)
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
@ -58,19 +58,19 @@ const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
#if (CSS_SGI_CHIP_COUNT > 1)
#if (NRD_CHIP_COUNT > 1)
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x0)),
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x1)),
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x2)),
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x3)),
#endif
#if (CSS_SGI_CHIP_COUNT > 2)
#if (NRD_CHIP_COUNT > 2)
(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x0)),
(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x1)),
(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x2)),
(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x3)),
#endif
#if (CSS_SGI_CHIP_COUNT > 3)
#if (NRD_CHIP_COUNT > 3)
(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x0)),
(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x1)),
(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x2)),

10
plat/arm/board/neoverse_rd/platform/sgi575/platform.mk
View file

@ -56,12 +56,12 @@ NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
# Add the NT_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
ifneq ($(CSS_SGI_CHIP_COUNT),1)
ifneq ($(NRD_CHIP_COUNT),1)
$(error "Chip count for SGI575 should be 1, currently set to \
${CSS_SGI_CHIP_COUNT}.")
${NRD_CHIP_COUNT}.")
endif
ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
$(error "CSS_SGI_PLATFORM_VARIANT for SGI575 should always be 0,\
currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
ifneq ($(NRD_PLATFORM_VARIANT),0)
$(error "NRD_PLATFORM_VARIANT for SGI575 should always be 0,\
currently set to ${NRD_PLATFORM_VARIANT}.")
endif