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fix(st-ddr): correct DDR warnings
Replace %d with %u in logs, to avoid warning when -Wformat-signedness is enabled. And correct the order of includes. Change-Id: I7c711a37fc1deceb8853831a8a09ae50422859c9 Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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64fc535972
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2 changed files with 11 additions and 12 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved
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* Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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*/
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@ -7,21 +7,21 @@
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#include <errno.h>
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#include <stddef.h>
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#include <platform_def.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/clk.h>
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#include <drivers/delay_timer.h>
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#include <drivers/st/stm32mp_pmic.h>
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#include <drivers/st/stm32mp1_ddr.h>
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#include <drivers/st/stm32mp1_ddr_regs.h>
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#include <drivers/st/stm32mp1_pwr.h>
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#include <drivers/st/stm32mp1_ram.h>
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#include <drivers/st/stm32mp_pmic.h>
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#include <lib/mmio.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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struct reg_desc {
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const char *name;
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uint16_t offset; /* Offset for base address */
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@ -729,7 +729,7 @@ void stm32mp1_ddr_init(struct ddr_info *priv,
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}
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VERBOSE("name = %s\n", config->info.name);
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VERBOSE("speed = %d kHz\n", config->info.speed);
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VERBOSE("speed = %u kHz\n", config->info.speed);
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VERBOSE("size = 0x%x\n", config->info.size);
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/* DDR INIT SEQUENCE */
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@ -1,15 +1,11 @@
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/*
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* Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved
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* Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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*/
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#include <errno.h>
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#include <libfdt.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <common/fdt_wrappers.h>
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@ -18,6 +14,9 @@
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#include <drivers/st/stm32mp1_ddr_helpers.h>
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#include <drivers/st/stm32mp1_ram.h>
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#include <lib/mmio.h>
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#include <libfdt.h>
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#include <platform_def.h>
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#define DDR_PATTERN 0xAAAAAAAAU
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#define DDR_ANTIPATTERN 0x55555555U
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@ -32,7 +31,7 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
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ddrphy_clk = clk_get_rate(DDRPHYC);
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VERBOSE("DDR: mem_speed (%d kHz), RCC %ld kHz\n",
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VERBOSE("DDR: mem_speed (%u kHz), RCC %lu kHz\n",
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mem_speed, ddrphy_clk / 1000U);
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mem_speed_hz = mem_speed * 1000U;
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@ -44,7 +43,7 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
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ddr_clk = mem_speed_hz - ddrphy_clk;
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}
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if (ddr_clk > (mem_speed_hz / 10)) {
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ERROR("DDR expected freq %d kHz, current is %ld kHz\n",
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ERROR("DDR expected freq %u kHz, current is %lu kHz\n",
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mem_speed, ddrphy_clk / 1000U);
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return -1;
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}
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