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chore(cpus): optimise runtime errata applications

Browse source 
The errata framework has a helper to invoke workarounds, complete with a
cpu rev_var check. We can use that directly instead of the
apply_cpu_pwr_dwn_errata to save on some code, as well as an extra
branch. It's also more readable.

Also, apply_erratum invocation in cpu files don't need to check the
rev_var as that was already done by the cpu_ops dispatcher for us to end
up in the file.

Finally, X2 erratum 2768515 only applies in the powerdown sequence, i.e.
at runtime. It doesn't achieve anything at reset, so we can label it
accordingly.

Change-Id: I02f9dd7d0619feb54c870938ea186be5e3a6ca7b
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
This commit is contained in:
Boyan Karatotev 2024-09-26 17:09:53 +01:00 • committed by Govindraj Raja
parent d981a3523c
commit 9f342211fa
16 changed files with 23 additions and 30 deletions
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2
include/lib/cpus/aarch64/cpu_macros.S
View file

@ -474,7 +474,7 @@
*
* _get_rev:
* Optional parameter that determines whether to insert a call to the CPU revision fetching
* procedure. Stores the result of this in the temporary register x10.
* procedure. Stores the result of this in the temporary register x10 to allow for chaining
*
* clobbers: x0-x10 (PCS compliant)
*/

2
lib/cpus/aarch64/cortex_a57.S
View file

@ -57,7 +57,7 @@ func cortex_a57_disable_ext_debug
msr osdlr_el1, x0
isb
apply_erratum cortex_a57, ERRATUM(817169), ERRATA_A57_817169
apply_erratum cortex_a57, ERRATUM(817169), ERRATA_A57_817169, NO_GET_CPU_REV
dsb sy
ret

2
lib/cpus/aarch64/cortex_a710.S
View file

@ -223,7 +223,7 @@ check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
* ----------------------------------------------------
*/
func cortex_a710_core_pwr_dwn
apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768
apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768, NO_GET_CPU_REV
apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219, NO_GET_CPU_REV
/* ---------------------------------------------------

2
lib/cpus/aarch64/cortex_a76.S
View file

@ -505,7 +505,7 @@ func cortex_a76_core_pwr_dwn
*/
sysreg_bit_set CORTEX_A76_CPUPWRCTLR_EL1, CORTEX_A76_CORE_PWRDN_EN_MASK
apply_erratum cortex_a76, ERRATUM(2743102), ERRATA_A76_2743102
apply_erratum cortex_a76, ERRATUM(2743102), ERRATA_A76_2743102, NO_GET_CPU_REV
isb
ret

2
lib/cpus/aarch64/cortex_a77.S
View file

@ -168,7 +168,7 @@ func cortex_a77_core_pwr_dwn
sysreg_bit_set CORTEX_A77_CPUPWRCTLR_EL1, \
CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
apply_erratum cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100
apply_erratum cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100, NO_GET_CPU_REV
isb
ret

2
lib/cpus/aarch64/cortex_a78.S
View file

@ -199,7 +199,7 @@ cpu_reset_func_end cortex_a78
func cortex_a78_core_pwr_dwn
sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019
apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019, NO_GET_CPU_REV
isb
ret

2
lib/cpus/aarch64/cortex_a78c.S
View file

@ -141,7 +141,7 @@ func cortex_a78c_core_pwr_dwn
*/
sysreg_bit_set CORTEX_A78C_CPUPWRCTLR_EL1, CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121
apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121, NO_GET_CPU_REV
isb
ret

11
lib/cpus/aarch64/cortex_x2.S
View file

@ -133,10 +133,10 @@ workaround_reset_end cortex_x2, ERRATUM(2742423)
check_erratum_ls cortex_x2, ERRATUM(2742423), CPU_REV(2, 1)
workaround_reset_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515
workaround_runtime_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515
/* dsb before isb of power down sequence */
dsb sy
workaround_reset_end cortex_x2, ERRATUM(2768515)
workaround_runtime_end cortex_x2, ERRATUM(2768515)
check_erratum_ls cortex_x2, ERRATUM(2768515), CPU_REV(2, 1)
@ -179,12 +179,7 @@ func cortex_x2_core_pwr_dwn
*/
sysreg_bit_set CORTEX_X2_CPUPWRCTLR_EL1, CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
#if ERRATA_X2_2768515
mov x15, x30
bl cpu_get_rev_var
bl erratum_cortex_x2_2768515_wa
mov x30, x15
#endif /* ERRATA_X2_2768515 */
apply_erratum cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515, NO_GET_CPU_REV
isb
ret
endfunc cortex_x2_core_pwr_dwn

4
lib/cpus/aarch64/cortex_x3.S
View file

@ -114,13 +114,13 @@ cpu_reset_func_end cortex_x3
* ----------------------------------------------------
*/
func cortex_x3_core_pwr_dwn
apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909, NO_GET_CPU_REV
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
apply_erratum cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088
apply_erratum cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088, NO_GET_CPU_REV
isb
ret
endfunc cortex_x3_core_pwr_dwn

2
lib/cpus/aarch64/cortex_x4.S
View file

@ -118,7 +118,7 @@ func cortex_x4_core_pwr_dwn
*/
sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089
apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089, NO_GET_CPU_REV
isb
ret

2
lib/cpus/aarch64/neoverse_n1.S
View file

@ -236,7 +236,7 @@ func neoverse_n1_core_pwr_dwn
*/
sysreg_bit_set NEOVERSE_N1_CPUPWRCTLR_EL1, NEOVERSE_N1_CORE_PWRDN_EN_MASK
apply_erratum neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102
apply_erratum neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102, NO_GET_CPU_REV
isb
ret

5
lib/cpus/aarch64/neoverse_n2.S
View file

@ -272,8 +272,7 @@ cpu_reset_func_start neoverse_n2
cpu_reset_func_end neoverse_n2
func neoverse_n2_core_pwr_dwn
apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478
apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478, NO_GET_CPU_REV
apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639, NO_GET_CPU_REV
/* ---------------------------------------------------
@ -283,7 +282,7 @@ func neoverse_n2_core_pwr_dwn
*/
sysreg_bit_set NEOVERSE_N2_CPUPWRCTLR_EL1, NEOVERSE_N2_CORE_PWRDN_EN_BIT
apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089
apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089, NO_GET_CPU_REV
isb
ret

2
lib/cpus/aarch64/neoverse_v1.S
View file

@ -260,7 +260,7 @@ func neoverse_v1_core_pwr_dwn
* ---------------------------------------------
*/
sysreg_bit_set NEOVERSE_V1_CPUPWRCTLR_EL1, NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
apply_erratum neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093
apply_erratum neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093, NO_GET_CPU_REV
isb
ret

2
lib/cpus/aarch64/neoverse_v2.S
View file

@ -107,7 +107,7 @@ func neoverse_v2_core_pwr_dwn
* ---------------------------------------------------
*/
sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372, NO_GET_CPU_REV
isb
ret

8
lib/psci/aarch64/psci_helpers.S
View file

@ -1,11 +1,12 @@
/*
* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <asm_macros.S>
#include <assert_macros.S>
#include <cpu_macros.S>
#include <lib/psci/psci.h>
#include <platform_def.h>
@ -124,9 +125,8 @@ endfunc psci_do_pwrup_cache_maintenance
* -----------------------------------------------------------------------
*/
func psci_power_down_wfi
#if ERRATA_A510_2684597
bl apply_cpu_pwr_dwn_errata
#endif
apply_erratum cortex_a510, ERRATUM(2684597), ERRATA_A510_2684597
dsb sy // ensure write buffer empty
wfi
no_ret plat_panic_handler

3
lib/psci/psci_lib.mk
View file

@ -21,8 +21,7 @@ PSCI_LIB_SOURCES := lib/el3_runtime/cpu_data_array.c \
lib/psci/${ARCH}/psci_helpers.S
ifeq (${ARCH}, aarch64)
PSCI_LIB_SOURCES += lib/el3_runtime/aarch64/context.S \
lib/cpus/aarch64/runtime_errata.S
PSCI_LIB_SOURCES += lib/el3_runtime/aarch64/context.S
endif
ifeq (${USE_COHERENT_MEM}, 1)