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Merge changes from topic "xlnx_fix_plat_data_types" into integration

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* changes:
  fix(versal2): typecast operands to match data type
  fix(versal): typecast operands to match data type
  fix(versal-net): typecast operands to match data type
  fix(xilinx): typecast operands to match data type
  fix(zynqmp): typecast operands to match data type
  fix(versal-net): typecast operands to match data type
  fix(versal): typecast operands to match data type
  fix(xilinx): typecast operands to match data type
  fix(zynqmp): typecast operands to match data type
  fix(versal2): typecast expressions to match data type
  fix(versal-net): typecast expressions to match data type
  fix(versal): typecast expressions to match data type
  fix(xilinx): typecast expressions to match data type
  fix(zynqmp): typecast expressions to match data type
  fix(zynqmp): align essential type categories
  fix(zynqmp): typecast expression to match data type
  fix(xilinx): typecast expression to match data type
This commit is contained in:
Joanna Farley 2024-12-23 09:52:49 +01:00 • committed by TrustedFirmware Code Review
commit 9ef62bd88d
36 changed files with 630 additions and 601 deletions
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4
plat/amd/versal2/aarch64/common.c
View file

@ -75,8 +75,8 @@ void board_detection(void)
uint32_t version_type; uint32_t version_type;
version_type = mmio_read_32(PMC_TAP_VERSION); version_type = mmio_read_32(PMC_TAP_VERSION);
platform_id = FIELD_GET(PLATFORM_MASK, version_type); platform_id = FIELD_GET((uint32_t)PLATFORM_MASK, version_type);
platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version_type); platform_version = FIELD_GET((uint32_t)PLATFORM_VERSION_MASK, version_type);
if (platform_id == QEMU_COSIM) { if (platform_id == QEMU_COSIM) {
platform_id = QEMU; platform_id = QEMU;

4
plat/amd/versal2/bl31_setup.c
View file

@ -63,7 +63,7 @@ static inline void bl31_set_default_config(void)
bl32_image_ep_info.args.arg3 = XILINX_OF_BOARD_DTB_ADDR; bl32_image_ep_info.args.arg3 = XILINX_OF_BOARD_DTB_ADDR;
#endif #endif
bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS); DISABLE_ALL_EXCEPTIONS);
} }
@ -229,7 +229,7 @@ void bl31_platform_setup(void)
void bl31_plat_runtime_setup(void) void bl31_plat_runtime_setup(void)
{ {
uint64_t flags = 0; uint32_t flags = 0;
int32_t rc; int32_t rc;
set_interrupt_rm_flag(flags, NON_SECURE); set_interrupt_rm_flag(flags, NON_SECURE);

2
plat/amd/versal2/include/def.h
View file

@ -12,7 +12,7 @@
#include <plat/arm/common/smccc_def.h> #include <plat/arm/common/smccc_def.h>
#include <plat/common/common_def.h> #include <plat/common/common_def.h>
#define MAX_INTR_EL3 2 #define MAX_INTR_EL3 2U
/* List all consoles */ /* List all consoles */
#define VERSAL2_CONSOLE_ID_none 0 #define VERSAL2_CONSOLE_ID_none 0

180
plat/amd/versal2/include/versal2-scmi.h
View file

@ -10,96 +10,96 @@
#ifndef _VERSAL2_SCMI_H #ifndef _VERSAL2_SCMI_H
#define _VERSAL2_SCMI_H #define _VERSAL2_SCMI_H
#define CLK_GEM0_0 0 #define CLK_GEM0_0 0U
#define CLK_GEM0_1 1 #define CLK_GEM0_1 1U
#define CLK_GEM0_2 2 #define CLK_GEM0_2 2U
#define CLK_GEM0_3 3 #define CLK_GEM0_3 3U
#define CLK_GEM0_4 4 #define CLK_GEM0_4 4U
#define CLK_GEM1_0 5 #define CLK_GEM1_0 5U
#define CLK_GEM1_1 6 #define CLK_GEM1_1 6U
#define CLK_GEM1_2 7 #define CLK_GEM1_2 7U
#define CLK_GEM1_3 8 #define CLK_GEM1_3 8U
#define CLK_GEM1_4 9 #define CLK_GEM1_4 9U
#define CLK_SERIAL0_0 10 #define CLK_SERIAL0_0 10U
#define CLK_SERIAL0_1 11 #define CLK_SERIAL0_1 11U
#define CLK_SERIAL1_0 12 #define CLK_SERIAL1_0 12U
#define CLK_SERIAL1_1 13 #define CLK_SERIAL1_1 13U
#define CLK_UFS0_0 14 #define CLK_UFS0_0 14U
#define CLK_UFS0_1 15 #define CLK_UFS0_1 15U
#define CLK_UFS0_2 16 #define CLK_UFS0_2 16U
#define CLK_USB0_0 17 #define CLK_USB0_0 17U
#define CLK_USB0_1 18 #define CLK_USB0_1 18U
#define CLK_USB0_2 19 #define CLK_USB0_2 19U
#define CLK_USB1_0 20 #define CLK_USB1_0 20U
#define CLK_USB1_1 21 #define CLK_USB1_1 21U
#define CLK_USB1_2 22 #define CLK_USB1_2 22U
#define CLK_MMC0_0 23 #define CLK_MMC0_0 23U
#define CLK_MMC0_1 24 #define CLK_MMC0_1 24U
#define CLK_MMC0_2 25 #define CLK_MMC0_2 25U
#define CLK_MMC1_0 26 #define CLK_MMC1_0 26U
#define CLK_MMC1_1 27 #define CLK_MMC1_1 27U
#define CLK_MMC1_2 28 #define CLK_MMC1_2 28U
#define CLK_TTC0_0 29 #define CLK_TTC0_0 29U
#define CLK_TTC1_0 30 #define CLK_TTC1_0 30U
#define CLK_TTC2_0 31 #define CLK_TTC2_0 31U
#define CLK_TTC3_0 32 #define CLK_TTC3_0 32U
#define CLK_TTC4_0 33 #define CLK_TTC4_0 33U
#define CLK_TTC5_0 34 #define CLK_TTC5_0 34U
#define CLK_TTC6_0 35 #define CLK_TTC6_0 35U
#define CLK_TTC7_0 36 #define CLK_TTC7_0 36U
#define CLK_I2C0_0 37 #define CLK_I2C0_0 37U
#define CLK_I2C1_0 38 #define CLK_I2C1_0 38U
#define CLK_I2C2_0 39 #define CLK_I2C2_0 39U
#define CLK_I2C3_0 40 #define CLK_I2C3_0 40U
#define CLK_I2C4_0 41 #define CLK_I2C4_0 41U
#define CLK_I2C5_0 42 #define CLK_I2C5_0 42U
#define CLK_I2C6_0 43 #define CLK_I2C6_0 43U
#define CLK_I2C7_0 44 #define CLK_I2C7_0 44U
#define CLK_OSPI0_0 45 #define CLK_OSPI0_0 45U
#define CLK_QSPI0_0 46 #define CLK_QSPI0_0 46U
#define CLK_QSPI0_1 47 #define CLK_QSPI0_1 47U
#define CLK_WWDT0_0 48 #define CLK_WWDT0_0 48U
#define CLK_WWDT1_0 49 #define CLK_WWDT1_0 49U
#define CLK_WWDT2_0 50 #define CLK_WWDT2_0 50U
#define CLK_WWDT3_0 51 #define CLK_WWDT3_0 51U
#define CLK_ADMA0_0 52 #define CLK_ADMA0_0 52U
#define CLK_ADMA0_1 53 #define CLK_ADMA0_1 53U
#define CLK_ADMA1_0 54 #define CLK_ADMA1_0 54U
#define CLK_ADMA1_1 55 #define CLK_ADMA1_1 55U
#define CLK_ADMA2_0 56 #define CLK_ADMA2_0 56U
#define CLK_ADMA2_1 57 #define CLK_ADMA2_1 57U
#define CLK_ADMA3_0 58 #define CLK_ADMA3_0 58U
#define CLK_ADMA3_1 59 #define CLK_ADMA3_1 59U
#define CLK_ADMA4_0 60 #define CLK_ADMA4_0 60U
#define CLK_ADMA4_1 61 #define CLK_ADMA4_1 61U
#define CLK_ADMA5_0 62 #define CLK_ADMA5_0 62U
#define CLK_ADMA5_1 63 #define CLK_ADMA5_1 63U
#define CLK_ADMA6_0 64 #define CLK_ADMA6_0 64U
#define CLK_ADMA6_1 65 #define CLK_ADMA6_1 65U
#define CLK_ADMA7_0 66 #define CLK_ADMA7_0 66U
#define CLK_ADMA7_1 67 #define CLK_ADMA7_1 67U
#define CLK_CAN0_0 68 #define CLK_CAN0_0 68U
#define CLK_CAN0_1 69 #define CLK_CAN0_1 69U
#define CLK_CAN1_0 70 #define CLK_CAN1_0 70U
#define CLK_CAN1_1 71 #define CLK_CAN1_1 71U
#define CLK_CAN2_0 72 #define CLK_CAN2_0 72U
#define CLK_CAN2_1 73 #define CLK_CAN2_1 73U
#define CLK_CAN3_0 74 #define CLK_CAN3_0 74U
#define CLK_CAN3_1 75 #define CLK_CAN3_1 75U
#define CLK_PS_GPIO_0 76 #define CLK_PS_GPIO_0 76U
#define CLK_PMC_GPIO_0 77 #define CLK_PMC_GPIO_0 77U
#define CLK_SPI0_0 78 #define CLK_SPI0_0 78U
#define CLK_SPI0_1 79 #define CLK_SPI0_1 79U
#define CLK_SPI1_0 80 #define CLK_SPI1_0 80U
#define CLK_SPI1_1 81 #define CLK_SPI1_1 81U
#define CLK_I3C0_0 82 #define CLK_I3C0_0 82U
#define CLK_I3C1_0 83 #define CLK_I3C1_0 83U
#define CLK_I3C2_0 84 #define CLK_I3C2_0 84U
#define CLK_I3C3_0 85 #define CLK_I3C3_0 85U
#define CLK_I3C4_0 86 #define CLK_I3C4_0 86U
#define CLK_I3C5_0 87 #define CLK_I3C5_0 87U
#define CLK_I3C6_0 88 #define CLK_I3C6_0 88U
#define CLK_I3C7_0 89 #define CLK_I3C7_0 89U
#define RESET_GEM0_0 0 #define RESET_GEM0_0 0
#define RESET_GEM1_0 1 #define RESET_GEM1_0 1

14
plat/amd/versal2/plat_psci.c
View file

@ -35,9 +35,9 @@ static void zynqmp_cpu_standby(plat_local_state_t cpu_state)
static int32_t zynqmp_nopmu_pwr_domain_on(u_register_t mpidr) static int32_t zynqmp_nopmu_pwr_domain_on(u_register_t mpidr)
{ {
uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr) & ~BIT(MPIDR_MT_BIT); int32_t cpu_id = plat_core_pos_by_mpidr(mpidr) & ~BIT(MPIDR_MT_BIT);
uint32_t cpu = cpu_id % PLATFORM_CORE_COUNT_PER_CLUSTER; int32_t cpu = cpu_id % PLATFORM_CORE_COUNT_PER_CLUSTER;
uint32_t cluster = cpu_id / PLATFORM_CORE_COUNT_PER_CLUSTER; int32_t cluster = cpu_id / PLATFORM_CORE_COUNT_PER_CLUSTER;
uintptr_t apu_cluster_base = 0, apu_pcli_base, apu_pcli_cluster = 0; uintptr_t apu_cluster_base = 0, apu_pcli_base, apu_pcli_cluster = 0;
uintptr_t rst_apu_cluster = PSX_CRF + RST_APU0_OFFSET + ((uint64_t)cluster * 0x4U); uintptr_t rst_apu_cluster = PSX_CRF + RST_APU0_OFFSET + ((uint64_t)cluster * 0x4U);
@ -48,7 +48,7 @@ static int32_t zynqmp_nopmu_pwr_domain_on(u_register_t mpidr)
return PSCI_E_INTERN_FAIL; return PSCI_E_INTERN_FAIL;
} }
if (cluster > 3) { if (cluster > 3U) {
panic(); panic();
} }
@ -69,7 +69,7 @@ static int32_t zynqmp_nopmu_pwr_domain_on(u_register_t mpidr)
mmio_write_32(apu_cluster_base + APU_RVBAR_L_0 + (cpu << 3), mmio_write_32(apu_cluster_base + APU_RVBAR_L_0 + (cpu << 3),
(uint32_t)_sec_entry); (uint32_t)_sec_entry);
mmio_write_32(apu_cluster_base + APU_RVBAR_H_0 + (cpu << 3), mmio_write_32(apu_cluster_base + APU_RVBAR_H_0 + (cpu << 3),
_sec_entry >> 32); (uint32_t)(_sec_entry >> 32));
/* de-assert core reset */ /* de-assert core reset */
mmio_clrbits_32(rst_apu_cluster, ((RST_APU_COLD_RESET|RST_APU_WARN_RESET) << cpu)); mmio_clrbits_32(rst_apu_cluster, ((RST_APU_COLD_RESET|RST_APU_WARN_RESET) << cpu));
@ -178,9 +178,9 @@ static int32_t no_pm_ioctl(uint32_t device_id, uint32_t ioctl_id,
ret = (int32_t) mmio_read_32(PMXC_IOU_SLCR_TX_RX_CONFIG_RDY); ret = (int32_t) mmio_read_32(PMXC_IOU_SLCR_TX_RX_CONFIG_RDY);
break; break;
case IOCTL_UFS_SRAM_CSR_SEL: case IOCTL_UFS_SRAM_CSR_SEL:
if (arg1 == 1) { if (arg1 == 1U) {
ret = (int32_t) mmio_read_32(PMXC_IOU_SLCR_SRAM_CSR); ret = (int32_t) mmio_read_32(PMXC_IOU_SLCR_SRAM_CSR);
} else if (arg1 == 0) { } else if (arg1 == 0U) {
mmio_write_32(PMXC_IOU_SLCR_SRAM_CSR, arg2); mmio_write_32(PMXC_IOU_SLCR_SRAM_CSR, arg2);
} }
break; break;

20
plat/amd/versal2/scmi.c
View file

@ -293,7 +293,7 @@ int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id,
return SCMI_NOT_FOUND; return SCMI_NOT_FOUND;
} }
if (start_idx > 0) { if (start_idx > 0U) {
return SCMI_OUT_OF_RANGE; return SCMI_OUT_OF_RANGE;
} }
@ -328,7 +328,7 @@ int32_t plat_scmi_clock_set_rate(unsigned int agent_id, unsigned int scmi_id,
unsigned long rate) unsigned long rate)
{ {
struct scmi_clk *clock = clk_find(agent_id, scmi_id); struct scmi_clk *clock = clk_find(agent_id, scmi_id);
unsigned long ret = UL(SCMI_SUCCESS); int32_t ret = SCMI_SUCCESS;
if ((clock == NULL)) { if ((clock == NULL)) {
ret = SCMI_NOT_FOUND; ret = SCMI_NOT_FOUND;
@ -564,17 +564,19 @@ int32_t plat_scmi_pd_set_state(unsigned int agent_id, unsigned int flags, unsign
unsigned int state) unsigned int state)
{ {
struct scmi_pd *pd = find_pd(agent_id, pd_id); struct scmi_pd *pd = find_pd(agent_id, pd_id);
int32_t ret = SCMI_SUCCESS;
if (pd == NULL) { if (pd == NULL) {
return SCMI_NOT_SUPPORTED; ret = SCMI_NOT_SUPPORTED;
} else {
NOTICE("SCMI: PD: set id: %d, orig state: %x, new state: %x, flags: %x\n",
pd_id, pd->state, state, flags);
pd->state = state;
} }
NOTICE("SCMI: PD: set id: %d, orig state: %x, new state: %x, flags: %x\n", return ret;
pd_id, pd->state, state, flags);
pd->state = state;
return 0U;
} }

2
plat/amd/versal2/sip_svc_setup.c
View file

@ -71,7 +71,7 @@ static uintptr_t sip_svc_smc_handler(uint32_t smc_fid,
VERBOSE("SMCID: 0x%08x, x1: 0x%016" PRIx64 ", x2: 0x%016" PRIx64 ", x3: 0x%016" PRIx64 ", x4: 0x%016" PRIx64 "\n", VERBOSE("SMCID: 0x%08x, x1: 0x%016" PRIx64 ", x2: 0x%016" PRIx64 ", x3: 0x%016" PRIx64 ", x4: 0x%016" PRIx64 "\n",
smc_fid, x1, x2, x3, x4); smc_fid, x1, x2, x3, x4);
if ((smc_fid & SIP_FID_MASK) != 0) { if ((smc_fid & SIP_FID_MASK) != 0U) {
WARN("SMC out of SiP assinged range: 0x%x\n", smc_fid); WARN("SMC out of SiP assinged range: 0x%x\n", smc_fid);
SMC_RET1(handle, SMC_UNK); SMC_RET1(handle, SMC_UNK);
} }

2
plat/xilinx/common/include/ipi.h
View file

@ -29,7 +29,7 @@
********************************************************************/ ********************************************************************/
#define IPI_SECURE_MASK (0x1U) #define IPI_SECURE_MASK (0x1U)
#define IPI_IS_SECURE(I) ((ipi_table[(I)].secure_only & \ #define IPI_IS_SECURE(I) ((ipi_table[(I)].secure_only & \
IPI_SECURE_MASK) ? 1 : 0) IPI_SECURE_MASK) ? true : false)
/********************************************************************* /*********************************************************************
* Struct definitions * Struct definitions

42
plat/xilinx/common/ipi.c
View file

@ -90,11 +90,11 @@ int ipi_mb_validate(uint32_t local, uint32_t remote, unsigned int is_secure)
{ {
int ret = 0; int ret = 0;
if (!is_ipi_mb_within_range(local, remote)) { if (is_ipi_mb_within_range(local, remote) == 0) {
ret = -EINVAL; ret = -EINVAL;
} else if (IPI_IS_SECURE(local) && !is_secure) { } else if (IPI_IS_SECURE(local) && (is_secure == 0U)) {
ret = -EPERM; ret = -EPERM;
} else if (IPI_IS_SECURE(remote) && !is_secure) { } else if (IPI_IS_SECURE(remote) && (is_secure == 0U)) {
ret = -EPERM; ret = -EPERM;
} else { } else {
/* To fix the misra 15.7 warning */ /* To fix the misra 15.7 warning */
@ -111,9 +111,12 @@ int ipi_mb_validate(uint32_t local, uint32_t remote, unsigned int is_secure)
*/ */
void ipi_mb_open(uint32_t local, uint32_t remote) void ipi_mb_open(uint32_t local, uint32_t remote)
{ {
mmio_write_32(IPI_REG_BASE(local) + IPI_IDR_OFFSET, uint64_t idr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_IDR_OFFSET);
uint64_t isr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_ISR_OFFSET);
mmio_write_32(idr_offset,
IPI_BIT_MASK(remote)); IPI_BIT_MASK(remote));
mmio_write_32(IPI_REG_BASE(local) + IPI_ISR_OFFSET, mmio_write_32(isr_offset,
IPI_BIT_MASK(remote)); IPI_BIT_MASK(remote));
} }
@ -125,7 +128,9 @@ void ipi_mb_open(uint32_t local, uint32_t remote)
*/ */
void ipi_mb_release(uint32_t local, uint32_t remote) void ipi_mb_release(uint32_t local, uint32_t remote)
{ {
mmio_write_32(IPI_REG_BASE(local) + IPI_IDR_OFFSET, uint64_t idr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_IDR_OFFSET);
mmio_write_32(idr_offset,
IPI_BIT_MASK(remote)); IPI_BIT_MASK(remote));
} }
@ -142,12 +147,14 @@ int ipi_mb_enquire_status(uint32_t local, uint32_t remote)
{ {
int ret = 0U; int ret = 0U;
uint32_t status; uint32_t status;
uint64_t obr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_OBR_OFFSET);
uint64_t isr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_ISR_OFFSET);
status = mmio_read_32(IPI_REG_BASE(local) + IPI_OBR_OFFSET); status = mmio_read_32(obr_offset);
if ((status & IPI_BIT_MASK(remote)) != 0U) { if ((status & IPI_BIT_MASK(remote)) != 0U) {
ret |= IPI_MB_STATUS_SEND_PENDING; ret |= IPI_MB_STATUS_SEND_PENDING;
} }
status = mmio_read_32(IPI_REG_BASE(local) + IPI_ISR_OFFSET); status = mmio_read_32(isr_offset);
if ((status & IPI_BIT_MASK(remote)) != 0U) { if ((status & IPI_BIT_MASK(remote)) != 0U) {
ret |= IPI_MB_STATUS_RECV_PENDING; ret |= IPI_MB_STATUS_RECV_PENDING;
} }
@ -167,13 +174,14 @@ int ipi_mb_enquire_status(uint32_t local, uint32_t remote)
void ipi_mb_notify(uint32_t local, uint32_t remote, uint32_t is_blocking) void ipi_mb_notify(uint32_t local, uint32_t remote, uint32_t is_blocking)
{ {
uint32_t status; uint32_t status;
uint64_t trig_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_TRIG_OFFSET);
uint64_t obr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_OBR_OFFSET);
mmio_write_32(IPI_REG_BASE(local) + IPI_TRIG_OFFSET, mmio_write_32(trig_offset,
IPI_BIT_MASK(remote)); IPI_BIT_MASK(remote));
if (is_blocking != 0U) { if (is_blocking != 0U) {
do { do {
status = mmio_read_32(IPI_REG_BASE(local) + status = mmio_read_32(obr_offset);
IPI_OBR_OFFSET);
} while ((status & IPI_BIT_MASK(remote)) != 0U); } while ((status & IPI_BIT_MASK(remote)) != 0U);
} }
} }
@ -188,7 +196,9 @@ void ipi_mb_notify(uint32_t local, uint32_t remote, uint32_t is_blocking)
*/ */
void ipi_mb_ack(uint32_t local, uint32_t remote) void ipi_mb_ack(uint32_t local, uint32_t remote)
{ {
mmio_write_32(IPI_REG_BASE(local) + IPI_ISR_OFFSET, uint64_t isr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_ISR_OFFSET);
mmio_write_32(isr_offset,
IPI_BIT_MASK(remote)); IPI_BIT_MASK(remote));
} }
@ -202,7 +212,9 @@ void ipi_mb_ack(uint32_t local, uint32_t remote)
*/ */
void ipi_mb_disable_irq(uint32_t local, uint32_t remote) void ipi_mb_disable_irq(uint32_t local, uint32_t remote)
{ {
mmio_write_32(IPI_REG_BASE(local) + IPI_IDR_OFFSET, uint64_t idr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_IDR_OFFSET);
mmio_write_32(idr_offset,
IPI_BIT_MASK(remote)); IPI_BIT_MASK(remote));
} }
@ -216,6 +228,8 @@ void ipi_mb_disable_irq(uint32_t local, uint32_t remote)
*/ */
void ipi_mb_enable_irq(uint32_t local, uint32_t remote) void ipi_mb_enable_irq(uint32_t local, uint32_t remote)
{ {
mmio_write_32(IPI_REG_BASE(local) + IPI_IER_OFFSET, uint64_t ier_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_IER_OFFSET);
mmio_write_32(ier_offset,
IPI_BIT_MASK(remote)); IPI_BIT_MASK(remote));
} }

16
plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
View file

@ -78,8 +78,8 @@ uint64_t ipi_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2,
uint32_t ipi_remote_id; uint32_t ipi_remote_id;
uint32_t is_secure; uint32_t is_secure;
ipi_local_id = x1 & UNSIGNED32_MASK; ipi_local_id = (uint32_t)(x1 & UNSIGNED32_MASK);
ipi_remote_id = x2 & UNSIGNED32_MASK; ipi_remote_id = (uint32_t)(x2 & UNSIGNED32_MASK);
/* OEN Number 48 to 63 is for Trusted App and OS /* OEN Number 48 to 63 is for Trusted App and OS
* GET_SMC_OEN limits the return value of OEN number to 63 by bitwise * GET_SMC_OEN limits the return value of OEN number to 63 by bitwise
@ -106,11 +106,11 @@ uint64_t ipi_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2,
SMC_RET1(handle, 0); SMC_RET1(handle, 0);
case IPI_MAILBOX_STATUS_ENQUIRY: case IPI_MAILBOX_STATUS_ENQUIRY:
{ {
int32_t disable_interrupt; bool disable_interrupt;
disable_interrupt = (x3 & IPI_SMC_ENQUIRY_DIRQ_MASK) ? 1 : 0; disable_interrupt = ((x3 & IPI_SMC_ENQUIRY_DIRQ_MASK) != 0U);
ret = ipi_mb_enquire_status(ipi_local_id, ipi_remote_id); ret = ipi_mb_enquire_status(ipi_local_id, ipi_remote_id);
if ((ret & IPI_MB_STATUS_RECV_PENDING) && disable_interrupt) if ((((uint32_t)ret & IPI_MB_STATUS_RECV_PENDING) > 0U) && disable_interrupt)
ipi_mb_disable_irq(ipi_local_id, ipi_remote_id); ipi_mb_disable_irq(ipi_local_id, ipi_remote_id);
SMC_RET1(handle, ret); SMC_RET1(handle, ret);
} }
@ -118,15 +118,15 @@ uint64_t ipi_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2,
{ {
uint32_t is_blocking; uint32_t is_blocking;
is_blocking = (x3 & IPI_SMC_NOTIFY_BLOCK_MASK) ? 1 : 0; is_blocking = ((x3 & IPI_SMC_NOTIFY_BLOCK_MASK) != 0U);
ipi_mb_notify(ipi_local_id, ipi_remote_id, is_blocking); ipi_mb_notify(ipi_local_id, ipi_remote_id, is_blocking);
SMC_RET1(handle, 0); SMC_RET1(handle, 0);
} }
case IPI_MAILBOX_ACK: case IPI_MAILBOX_ACK:
{ {
int32_t enable_interrupt; bool enable_interrupt;
enable_interrupt = (x3 & IPI_SMC_ACK_EIRQ_MASK) ? 1 : 0; enable_interrupt = ((x3 & IPI_SMC_ACK_EIRQ_MASK) != 0U);
ipi_mb_ack(ipi_local_id, ipi_remote_id); ipi_mb_ack(ipi_local_id, ipi_remote_id);
if (enable_interrupt != 0) if (enable_interrupt != 0)
ipi_mb_enable_irq(ipi_local_id, ipi_remote_id); ipi_mb_enable_irq(ipi_local_id, ipi_remote_id);

52
plat/xilinx/common/plat_startup.c
View file

@ -72,11 +72,13 @@
* Return: XBL_FLAGS_A53_0, XBL_FLAGS_A53_1, XBL_FLAGS_A53_2 or XBL_FLAGS_A53_3. * Return: XBL_FLAGS_A53_0, XBL_FLAGS_A53_1, XBL_FLAGS_A53_2 or XBL_FLAGS_A53_3.
* *
*/ */
static int32_t get_xbl_cpu(const struct xbl_partition *partition) static uint32_t get_xbl_cpu(const struct xbl_partition *partition)
{ {
uint64_t flags = partition->flags & XBL_FLAGS_CPU_MASK; uint64_t flags = partition->flags & XBL_FLAGS_CPU_MASK;
return flags >> XBL_FLAGS_CPU_SHIFT; flags >>= XBL_FLAGS_CPU_SHIFT;
return (uint32_t)flags;
} }
/** /**
@ -86,11 +88,13 @@ static int32_t get_xbl_cpu(const struct xbl_partition *partition)
* Return: XBL_FLAGS_EL0, XBL_FLAGS_EL1, XBL_FLAGS_EL2 or XBL_FLAGS_EL3. * Return: XBL_FLAGS_EL0, XBL_FLAGS_EL1, XBL_FLAGS_EL2 or XBL_FLAGS_EL3.
* *
*/ */
static int32_t get_xbl_el(const struct xbl_partition *partition) static uint32_t get_xbl_el(const struct xbl_partition *partition)
{ {
uint64_t flags = partition->flags & XBL_FLAGS_EL_MASK; uint64_t flags = partition->flags & XBL_FLAGS_EL_MASK;
return flags >> XBL_FLAGS_EL_SHIFT; flags >>= XBL_FLAGS_EL_SHIFT;
return (uint32_t)flags;
} }
/** /**
@ -100,11 +104,13 @@ static int32_t get_xbl_el(const struct xbl_partition *partition)
* Return: XBL_FLAGS_NON_SECURE or XBL_FLAGS_SECURE. * Return: XBL_FLAGS_NON_SECURE or XBL_FLAGS_SECURE.
* *
*/ */
static int32_t get_xbl_ss(const struct xbl_partition *partition) static uint32_t get_xbl_ss(const struct xbl_partition *partition)
{ {
uint64_t flags = partition->flags & XBL_FLAGS_TZ_MASK; uint64_t flags = partition->flags & XBL_FLAGS_TZ_MASK;
return flags >> XBL_FLAGS_TZ_SHIFT; flags >>= XBL_FLAGS_TZ_SHIFT;
return (uint32_t)flags;
} }
/** /**
@ -114,7 +120,7 @@ static int32_t get_xbl_ss(const struct xbl_partition *partition)
* Return: SPSR_E_LITTLE or SPSR_E_BIG. * Return: SPSR_E_LITTLE or SPSR_E_BIG.
* *
*/ */
static int32_t get_xbl_endian(const struct xbl_partition *partition) static uint32_t get_xbl_endian(const struct xbl_partition *partition)
{ {
uint64_t flags = partition->flags & XBL_FLAGS_ENDIAN_MASK; uint64_t flags = partition->flags & XBL_FLAGS_ENDIAN_MASK;
@ -134,11 +140,13 @@ static int32_t get_xbl_endian(const struct xbl_partition *partition)
* Return: XBL_FLAGS_ESTATE_A32 or XBL_FLAGS_ESTATE_A64. * Return: XBL_FLAGS_ESTATE_A32 or XBL_FLAGS_ESTATE_A64.
* *
*/ */
static int32_t get_xbl_estate(const struct xbl_partition *partition) static uint32_t get_xbl_estate(const struct xbl_partition *partition)
{ {
uint64_t flags = partition->flags & XBL_FLAGS_ESTATE_MASK; uint64_t flags = partition->flags & XBL_FLAGS_ESTATE_MASK;
return flags >> XBL_FLAGS_ESTATE_SHIFT; flags >>= XBL_FLAGS_ESTATE_SHIFT;
return flags;
} }
#if defined(PLAT_versal_net) #if defined(PLAT_versal_net)
@ -148,11 +156,11 @@ static int32_t get_xbl_estate(const struct xbl_partition *partition)
* *
* Return: cluster number for the partition. * Return: cluster number for the partition.
*/ */
static int32_t get_xbl_cluster(const struct xbl_partition *partition) static uint32_t get_xbl_cluster(const struct xbl_partition *partition)
{ {
uint64_t flags = partition->flags & XBL_FLAGS_CLUSTER_MASK; uint64_t flags = partition->flags & XBL_FLAGS_CLUSTER_MASK;
return (int32_t)(flags >> XBL_FLAGS_CLUSTER_SHIFT); return (flags >> XBL_FLAGS_CLUSTER_SHIFT);
} }
#endif /* PLAT_versal_net */ #endif /* PLAT_versal_net */
@ -175,16 +183,16 @@ enum xbl_handoff xbl_handover(entry_point_info_t *bl32,
{ {
const struct xbl_handoff_params *HandoffParams; const struct xbl_handoff_params *HandoffParams;
if (!handoff_addr) { if (handoff_addr == 0U) {
WARN("BL31: No handoff structure passed\n"); WARN("BL31: No handoff structure passed\n");
return XBL_HANDOFF_NO_STRUCT; return XBL_HANDOFF_NO_STRUCT;
} }
HandoffParams = (struct xbl_handoff_params *)handoff_addr; HandoffParams = (struct xbl_handoff_params *)handoff_addr;
if ((HandoffParams->magic[0] != 'X') || if ((HandoffParams->magic[0] != (uint8_t)'X') ||
(HandoffParams->magic[1] != 'L') || (HandoffParams->magic[1] != (uint8_t)'L') ||
(HandoffParams->magic[2] != 'N') || (HandoffParams->magic[2] != (uint8_t)'N') ||
(HandoffParams->magic[3] != 'X')) { (HandoffParams->magic[3] != (uint8_t)'X')) {
ERROR("BL31: invalid handoff structure at %" PRIx64 "\n", handoff_addr); ERROR("BL31: invalid handoff structure at %" PRIx64 "\n", handoff_addr);
return XBL_HANDOFF_INVAL_STRUCT; return XBL_HANDOFF_INVAL_STRUCT;
} }
@ -204,7 +212,7 @@ enum xbl_handoff xbl_handover(entry_point_info_t *bl32,
*/ */
for (size_t i = 0; i < HandoffParams->num_entries; i++) { for (size_t i = 0; i < HandoffParams->num_entries; i++) {
entry_point_info_t *image; entry_point_info_t *image;
int32_t target_estate, target_secure, target_cpu; uint32_t target_estate, target_secure, target_cpu;
uint32_t target_endianness, target_el; uint32_t target_endianness, target_el;
VERBOSE("BL31: %zd: entry:0x%" PRIx64 ", flags:0x%" PRIx64 "\n", i, VERBOSE("BL31: %zd: entry:0x%" PRIx64 ", flags:0x%" PRIx64 "\n", i,
@ -251,8 +259,8 @@ enum xbl_handoff xbl_handover(entry_point_info_t *bl32,
image = bl32; image = bl32;
if (target_estate == XBL_FLAGS_ESTATE_A32) { if (target_estate == XBL_FLAGS_ESTATE_A32) {
bl32->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM, bl32->spsr = (uint32_t)SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
target_endianness, (uint64_t)target_endianness,
DISABLE_ALL_EXCEPTIONS); DISABLE_ALL_EXCEPTIONS);
} else { } else {
bl32->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, bl32->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
@ -268,8 +276,8 @@ enum xbl_handoff xbl_handover(entry_point_info_t *bl32,
target_el = MODE32_sys; target_el = MODE32_sys;
} }
bl33->spsr = SPSR_MODE32(target_el, SPSR_T_ARM, bl33->spsr = (uint32_t)SPSR_MODE32((uint64_t)target_el, SPSR_T_ARM,
target_endianness, (uint64_t)target_endianness,
DISABLE_ALL_EXCEPTIONS); DISABLE_ALL_EXCEPTIONS);
} else { } else {
if (target_el == XBL_FLAGS_EL2) { if (target_el == XBL_FLAGS_EL2) {
@ -278,7 +286,7 @@ enum xbl_handoff xbl_handover(entry_point_info_t *bl32,
target_el = MODE_EL1; target_el = MODE_EL1;
} }
bl33->spsr = SPSR_64(target_el, MODE_SP_ELX, bl33->spsr = (uint32_t)SPSR_64((uint64_t)target_el, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS); DISABLE_ALL_EXCEPTIONS);
} }
} }

13
plat/xilinx/common/pm_service/pm_api_sys.c
View file

@ -56,7 +56,8 @@ void pm_client_set_wakeup_sources(uint32_t node_id)
for (reg_num = 0U; reg_num < NUM_GICD_ISENABLER; reg_num++) { for (reg_num = 0U; reg_num < NUM_GICD_ISENABLER; reg_num++) {
uint32_t base_irq = reg_num << ISENABLER_SHIFT; uint32_t base_irq = reg_num << ISENABLER_SHIFT;
uint32_t reg = mmio_read_32(isenabler1 + (reg_num << 2)); isenabler1 += (reg_num << 2);
uint32_t reg = mmio_read_32((uint64_t)isenabler1);
if (reg == 0U) { if (reg == 0U) {
continue; continue;
@ -117,7 +118,7 @@ enum pm_ret_status pm_handle_eemi_call(uint32_t flag, uint32_t x0, uint32_t x1,
module_id = (x0 & MODULE_ID_MASK) >> 8U; module_id = (x0 & MODULE_ID_MASK) >> 8U;
//default module id is for LIBPM //default module id is for LIBPM
if (module_id == 0) { if (module_id == 0U) {
module_id = LIBPM_MODULE_ID; module_id = LIBPM_MODULE_ID;
} }
@ -218,7 +219,7 @@ enum pm_ret_status pm_req_suspend(uint32_t target, uint8_t ack,
/* Send request to the PMU */ /* Send request to the PMU */
PM_PACK_PAYLOAD4(payload, LIBPM_MODULE_ID, flag, PM_REQ_SUSPEND, target, PM_PACK_PAYLOAD4(payload, LIBPM_MODULE_ID, flag, PM_REQ_SUSPEND, target,
latency, state); latency, state);
if (ack == IPI_BLOCKING) { if (ack == (uint32_t)IPI_BLOCKING) {
return pm_ipi_send_sync(primary_proc, payload, NULL, 0); return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
} else { } else {
return pm_ipi_send(primary_proc, payload); return pm_ipi_send(primary_proc, payload);
@ -273,7 +274,7 @@ enum pm_ret_status pm_get_callbackdata(uint32_t *data, size_t count, uint32_t fl
{ {
enum pm_ret_status ret = PM_RET_SUCCESS; enum pm_ret_status ret = PM_RET_SUCCESS;
/* Return if interrupt is not from PMU */ /* Return if interrupt is not from PMU */
if (pm_ipi_irq_status(primary_proc) == 0) { if (pm_ipi_irq_status(primary_proc) == 0U) {
return ret; return ret;
} }
@ -306,7 +307,7 @@ enum pm_ret_status pm_force_powerdown(uint32_t target, uint8_t ack,
PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, flag, PM_FORCE_POWERDOWN, PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, flag, PM_FORCE_POWERDOWN,
target, ack); target, ack);
if (ack == IPI_BLOCKING) { if (ack == (uint32_t)IPI_BLOCKING) {
return pm_ipi_send_sync(primary_proc, payload, NULL, 0); return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
} else { } else {
return pm_ipi_send(primary_proc, payload); return pm_ipi_send(primary_proc, payload);
@ -431,7 +432,7 @@ enum pm_ret_status pm_feature_check(uint32_t api_id, uint32_t *ret_payload,
* feature check should be done only for LIBPM module * feature check should be done only for LIBPM module
* If module_id is 0, then we consider it LIBPM module as default id * If module_id is 0, then we consider it LIBPM module as default id
*/ */
if ((module_id > 0) && (module_id != LIBPM_MODULE_ID)) { if ((module_id > 0U) && (module_id != LIBPM_MODULE_ID)) {
return PM_RET_SUCCESS; return PM_RET_SUCCESS;
} }

6
plat/xilinx/common/pm_service/pm_ipi.c
View file

@ -226,7 +226,7 @@ enum pm_ret_status pm_ipi_buff_read_callb(uint32_t *value, size_t count)
IPI_BUFFER_REQ_OFFSET; IPI_BUFFER_REQ_OFFSET;
enum pm_ret_status ret = PM_RET_SUCCESS; enum pm_ret_status ret = PM_RET_SUCCESS;
if (local_count > IPI_BUFFER_MAX_WORDS) { if (local_count > (uint32_t)IPI_BUFFER_MAX_WORDS) {
local_count = IPI_BUFFER_MAX_WORDS; local_count = IPI_BUFFER_MAX_WORDS;
} }
@ -273,7 +273,7 @@ enum pm_ret_status pm_ipi_send_sync(const struct pm_proc *proc,
goto unlock; goto unlock;
} }
ret = ERROR_CODE_MASK & (pm_ipi_buff_read(proc, value, count)); ret = ERROR_CODE_MASK & (uint32_t)(pm_ipi_buff_read(proc, value, count));
unlock: unlock:
pm_ipi_lock_release(); pm_ipi_lock_release();
@ -297,7 +297,7 @@ uint32_t pm_ipi_irq_status(const struct pm_proc *proc)
ret = ipi_mb_enquire_status(proc->ipi->local_ipi_id, ret = ipi_mb_enquire_status(proc->ipi->local_ipi_id,
proc->ipi->remote_ipi_id); proc->ipi->remote_ipi_id);
if (ret & IPI_MB_STATUS_RECV_PENDING) { if (((uint32_t)ret & IPI_MB_STATUS_RECV_PENDING) != 0U) {
return 1; return 1;
} else { } else {
return 0; return 0;

18
plat/xilinx/common/pm_service/pm_svc_main.c
View file

@ -113,7 +113,7 @@ void request_cpu_pwrdwn(void)
/* Send powerdown request to online secondary core(s) */ /* Send powerdown request to online secondary core(s) */
ret = psci_stop_other_cores(PWRDWN_WAIT_TIMEOUT, raise_pwr_down_interrupt); ret = psci_stop_other_cores(PWRDWN_WAIT_TIMEOUT, raise_pwr_down_interrupt);
if (ret != PSCI_E_SUCCESS) { if (ret != (uint32_t)PSCI_E_SUCCESS) {
ERROR("Failed to powerdown secondary core(s)\n"); ERROR("Failed to powerdown secondary core(s)\n");
} }
@ -140,11 +140,11 @@ static uint64_t ipi_fiq_handler(uint32_t id, uint32_t flags, void *handle,
(void)plat_ic_acknowledge_interrupt(); (void)plat_ic_acknowledge_interrupt();
/* Check status register for each IPI except PMC */ /* Check status register for each IPI except PMC */
for (i = IPI_ID_APU; i <= IPI_ID_5; i++) { for (i = (int32_t)IPI_ID_APU; i <= IPI_ID_5; i++) {
ipi_status = ipi_mb_enquire_status(IPI_ID_APU, i); ipi_status = ipi_mb_enquire_status(IPI_ID_APU, i);
/* If any agent other than PMC has generated IPI FIQ then send SGI to mbox driver */ /* If any agent other than PMC has generated IPI FIQ then send SGI to mbox driver */
if (ipi_status & IPI_MB_STATUS_RECV_PENDING) { if ((uint32_t)ipi_status & IPI_MB_STATUS_RECV_PENDING) {
plat_ic_raise_ns_sgi(MBOX_SGI_SHARED_IPI, read_mpidr_el1()); plat_ic_raise_ns_sgi(MBOX_SGI_SHARED_IPI, read_mpidr_el1());
break; break;
} }
@ -152,7 +152,7 @@ static uint64_t ipi_fiq_handler(uint32_t id, uint32_t flags, void *handle,
/* If PMC has not generated interrupt then end ISR */ /* If PMC has not generated interrupt then end ISR */
ipi_status = ipi_mb_enquire_status(IPI_ID_APU, IPI_ID_PMC); ipi_status = ipi_mb_enquire_status(IPI_ID_APU, IPI_ID_PMC);
if ((ipi_status & IPI_MB_STATUS_RECV_PENDING) == 0) { if (((uint32_t)ipi_status & IPI_MB_STATUS_RECV_PENDING) == 0U) {
plat_ic_end_of_interrupt(id); plat_ic_end_of_interrupt(id);
return 0; return 0;
} }
@ -160,7 +160,7 @@ static uint64_t ipi_fiq_handler(uint32_t id, uint32_t flags, void *handle,
/* Handle PMC case */ /* Handle PMC case */
ret = pm_get_callbackdata(payload, ARRAY_SIZE(payload), 0, 0); ret = pm_get_callbackdata(payload, ARRAY_SIZE(payload), 0, 0);
if (ret != PM_RET_SUCCESS) { if (ret != PM_RET_SUCCESS) {
payload[0] = ret; payload[0] = (uint32_t)ret;
} }
switch (payload[0]) { switch (payload[0]) {
@ -278,7 +278,7 @@ int32_t pm_setup(void)
gicd_write_irouter(gicv3_driver_data->gicd_base, PLAT_VERSAL_IPI_IRQ, MODE); gicd_write_irouter(gicv3_driver_data->gicd_base, PLAT_VERSAL_IPI_IRQ, MODE);
/* Register for idle callback during force power down/restart */ /* Register for idle callback during force power down/restart */
ret = pm_register_notifier(primary_proc->node_id, EVENT_CPU_PWRDWN, ret = (int32_t)pm_register_notifier(primary_proc->node_id, EVENT_CPU_PWRDWN,
0x0U, 0x1U, SECURE_FLAG); 0x0U, 0x1U, SECURE_FLAG);
if (ret != 0) { if (ret != 0) {
WARN("BL31: registering idle callback for restart/force power down failed\n"); WARN("BL31: registering idle callback for restart/force power down failed\n");
@ -428,7 +428,7 @@ static uintptr_t TF_A_specific_handler(uint32_t api_id, uint32_t *pm_arg,
ret = pm_get_callbackdata(result, ARRAY_SIZE(result), security_flag, 1U); ret = pm_get_callbackdata(result, ARRAY_SIZE(result), security_flag, 1U);
if (ret != 0) { if (ret != 0) {
result[0] = ret; result[0] = (uint32_t)ret;
} }
SMC_RET2(handle, SMC_RET2(handle,
@ -478,8 +478,8 @@ static uintptr_t eemi_handler(uint32_t api_id, uint32_t *pm_arg,
* than other eemi calls. * than other eemi calls.
*/ */
if (api_id == (uint32_t)PM_QUERY_DATA) { if (api_id == (uint32_t)PM_QUERY_DATA) {
if (((pm_arg[0] == XPM_QID_CLOCK_GET_NAME) || if (((pm_arg[0] == (uint32_t)XPM_QID_CLOCK_GET_NAME) ||
(pm_arg[0] == XPM_QID_PINCTRL_GET_FUNCTION_NAME)) && (pm_arg[0] == (uint32_t)XPM_QID_PINCTRL_GET_FUNCTION_NAME)) &&
(ret == PM_RET_SUCCESS)) { (ret == PM_RET_SUCCESS)) {
SMC_RET2(handle, (uint64_t)buf[0] | ((uint64_t)buf[1] << 32U), SMC_RET2(handle, (uint64_t)buf[0] | ((uint64_t)buf[1] << 32U),
(uint64_t)buf[2] | ((uint64_t)buf[3] << 32U)); (uint64_t)buf[2] | ((uint64_t)buf[3] << 32U));

2
plat/xilinx/common/versal.c
View file

@ -60,5 +60,5 @@ int32_t plat_get_soc_version(void)
*/ */
int32_t plat_get_soc_revision(void) int32_t plat_get_soc_revision(void)
{ {
return (platform_id & SOC_ID_REV_MASK); return (int32_t)(platform_id & SOC_ID_REV_MASK);
} }

2
plat/xilinx/versal/bl31_versal_setup.c
View file

@ -117,7 +117,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1, PM_LOAD_GET_HANDOFF_PARAMS, PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1U, PM_LOAD_GET_HANDOFF_PARAMS,
(uintptr_t)addr >> 32U, (uintptr_t)addr, max_size); (uintptr_t)addr >> 32U, (uintptr_t)addr, max_size);
ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0); ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0);
if (ret_status == PM_RET_SUCCESS) { if (ret_status == PM_RET_SUCCESS) {

2
plat/xilinx/versal/include/versal_def.h
View file

@ -16,7 +16,7 @@
#define PLATFORM_VERSION_MASK GENMASK(31U, 28U) #define PLATFORM_VERSION_MASK GENMASK(31U, 28U)
/* number of interrupt handlers. increase as required */ /* number of interrupt handlers. increase as required */
#define MAX_INTR_EL3 2 #define MAX_INTR_EL3 2U
/* List all consoles */ /* List all consoles */
#define VERSAL_CONSOLE_ID_none 0 #define VERSAL_CONSOLE_ID_none 0
#define VERSAL_CONSOLE_ID_pl011 1 #define VERSAL_CONSOLE_ID_pl011 1

2
plat/xilinx/versal/plat_psci.c
View file

@ -222,7 +222,7 @@ static void versal_pwr_domain_off(const psci_power_state_t *target_state)
* be set. * be set.
*/ */
ret = pm_feature_check((uint32_t)PM_SELF_SUSPEND, &version_type[0], SECURE_FLAG); ret = pm_feature_check((uint32_t)PM_SELF_SUSPEND, &version_type[0], SECURE_FLAG);
if (ret == PM_RET_SUCCESS) { if (ret == (uint32_t)PM_RET_SUCCESS) {
fw_api_version = version_type[0] & 0xFFFFU; fw_api_version = version_type[0] & 0xFFFFU;
if (fw_api_version >= 3U) { if (fw_api_version >= 3U) {
(void)pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_OFF, 0, (void)pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_OFF, 0,

12
plat/xilinx/versal/pm_service/pm_client.c
View file

@ -26,7 +26,7 @@
#include "pm_defs.h" #include "pm_defs.h"
#include <versal_def.h> #include <versal_def.h>
#define UNDEFINED_CPUID (~0) #define UNDEFINED_CPUID (~0U)
DEFINE_BAKERY_LOCK(pm_client_secure_lock); DEFINE_BAKERY_LOCK(pm_client_secure_lock);
@ -232,12 +232,16 @@ void pm_client_abort_suspend(void)
*/ */
static uint32_t pm_get_cpuid(uint32_t nid) static uint32_t pm_get_cpuid(uint32_t nid)
{ {
for (size_t i = 0U; i < ARRAY_SIZE(pm_procs_all); i++) { uint32_t ret = UNDEFINED_CPUID;
uint32_t i;
for (i = 0U; i < ARRAY_SIZE(pm_procs_all); i++) {
if (pm_procs_all[i].node_id == nid) { if (pm_procs_all[i].node_id == nid) {
return i; ret = i;
break;
} }
} }
return UNDEFINED_CPUID; return ret;
} }
/** /**

4
plat/xilinx/versal_net/bl31_versal_net_setup.c
View file

@ -55,7 +55,7 @@ static inline void bl31_set_default_config(void)
bl32_image_ep_info.pc = BL32_BASE; bl32_image_ep_info.pc = BL32_BASE;
bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS); DISABLE_ALL_EXCEPTIONS);
} }
@ -140,7 +140,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
#if !(TFA_NO_PM) #if !(TFA_NO_PM)
PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1, PM_LOAD_GET_HANDOFF_PARAMS, PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1U, PM_LOAD_GET_HANDOFF_PARAMS,
(uintptr_t)buff >> 32U, (uintptr_t)buff, max_size); (uintptr_t)buff >> 32U, (uintptr_t)buff, max_size);
ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0); ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0);

2
plat/xilinx/versal_net/include/versal_net_def.h
View file

@ -12,7 +12,7 @@
#include <plat/arm/common/smccc_def.h> #include <plat/arm/common/smccc_def.h>
#include <plat/common/common_def.h> #include <plat/common/common_def.h>
#define MAX_INTR_EL3 2 #define MAX_INTR_EL3 2U
/* List all consoles */ /* List all consoles */
#define VERSAL_NET_CONSOLE_ID_none U(0) #define VERSAL_NET_CONSOLE_ID_none U(0)

6
plat/xilinx/versal_net/plat_psci_pm.c
View file

@ -27,7 +27,7 @@ static uintptr_t versal_net_sec_entry;
static int32_t versal_net_pwr_domain_on(u_register_t mpidr) static int32_t versal_net_pwr_domain_on(u_register_t mpidr)
{ {
uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); int32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
const struct pm_proc *proc; const struct pm_proc *proc;
VERBOSE("%s: mpidr: 0x%lx, cpuid: %x\n", VERBOSE("%s: mpidr: 0x%lx, cpuid: %x\n",
@ -84,7 +84,7 @@ static void versal_net_pwr_domain_off(const psci_power_state_t *target_state)
* be set. * be set.
*/ */
ret = pm_feature_check((uint32_t)PM_SELF_SUSPEND, &version_type[0], SECURE_FLAG); ret = pm_feature_check((uint32_t)PM_SELF_SUSPEND, &version_type[0], SECURE_FLAG);
if (ret == PM_RET_SUCCESS) { if (ret == (uint32_t)PM_RET_SUCCESS) {
fw_api_version = version_type[0] & 0xFFFFU; fw_api_version = version_type[0] & 0xFFFFU;
if (fw_api_version >= 3U) { if (fw_api_version >= 3U) {
(void)pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_OFF, 0, (void)pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_OFF, 0,
@ -245,7 +245,7 @@ static int32_t versal_net_validate_power_state(unsigned int power_state,
{ {
VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
int32_t pstate = psci_get_pstate_type(power_state); uint32_t pstate = psci_get_pstate_type(power_state);
assert(req_state != NULL); assert(req_state != NULL);

6
plat/xilinx/versal_net/plat_topology.c
View file

@ -44,8 +44,8 @@ int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
mpidr &= MPIDR_AFFINITY_MASK; mpidr &= MPIDR_AFFINITY_MASK;
cluster_id = MPIDR_AFFLVL2_VAL(mpidr); cluster_id = (uint32_t)MPIDR_AFFLVL2_VAL(mpidr);
cpu_id = MPIDR_AFFLVL1_VAL(mpidr); cpu_id = (uint32_t)MPIDR_AFFLVL1_VAL(mpidr);
if (cluster_id >= PLATFORM_CLUSTER_COUNT) { if (cluster_id >= PLATFORM_CLUSTER_COUNT) {
return -3; return -3;
@ -59,5 +59,5 @@ int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
return -1; return -1;
} }
return (cpu_id + (cluster_id * PLATFORM_CORE_COUNT_PER_CLUSTER)); return (int32_t)(cpu_id + (cluster_id * PLATFORM_CORE_COUNT_PER_CLUSTER));
} }

12
plat/xilinx/versal_net/pm_service/pm_client.c
View file

@ -26,7 +26,7 @@
#include "pm_client.h" #include "pm_client.h"
#include <versal_net_def.h> #include <versal_net_def.h>
#define UNDEFINED_CPUID (~0) #define UNDEFINED_CPUID (~0U)
DEFINE_RENAME_SYSREG_RW_FUNCS(cpu_pwrctrl_val, S3_0_C15_C2_7) DEFINE_RENAME_SYSREG_RW_FUNCS(cpu_pwrctrl_val, S3_0_C15_C2_7)
@ -340,12 +340,16 @@ void pm_client_suspend(const struct pm_proc *proc, uint32_t state)
*/ */
static uint32_t pm_get_cpuid(uint32_t nid) static uint32_t pm_get_cpuid(uint32_t nid)
{ {
for (size_t i = 0; i < ARRAY_SIZE(pm_procs_all); i++) { uint32_t ret = UNDEFINED_CPUID;
uint32_t i;
for (i = 0; i < ARRAY_SIZE(pm_procs_all); i++) {
if (pm_procs_all[i].node_id == nid) { if (pm_procs_all[i].node_id == nid) {
return i; ret = i;
break;
} }
} }
return UNDEFINED_CPUID; return ret;
} }
/** /**

17
plat/xilinx/zynqmp/aarch64/zynqmp_common.c
View file

@ -42,9 +42,9 @@ const mmap_region_t *plat_get_mmap(void)
static uint32_t zynqmp_get_silicon_ver(void) static uint32_t zynqmp_get_silicon_ver(void)
{ {
static unsigned int ver; static uint32_t ver;
if (!ver) { if (ver == 0U) {
ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ver = mmio_read_32(ZYNQMP_CSU_BASEADDR +
ZYNQMP_CSU_VERSION_OFFSET); ZYNQMP_CSU_VERSION_OFFSET);
ver &= ZYNQMP_SILICON_VER_MASK; ver &= ZYNQMP_SILICON_VER_MASK;
@ -270,7 +270,7 @@ static char *zynqmp_get_silicon_idcode_name(void)
return zynqmp_devices[i].name; return zynqmp_devices[i].name;
} }
len = strlen(zynqmp_devices[i].name) - 2; len = strlen(zynqmp_devices[i].name) - 2U;
for (j = 0; j < strlen(name); j++) { for (j = 0; j < strlen(name); j++) {
zynqmp_devices[i].name[len] = name[j]; zynqmp_devices[i].name[len] = name[j];
len++; len++;
@ -326,13 +326,14 @@ int32_t plat_get_soc_version(void)
{ {
uint32_t chip_id = zynqmp_get_silicon_ver(); uint32_t chip_id = zynqmp_get_silicon_ver();
uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_XILINX_BKID, JEDEC_XILINX_MFID); uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_XILINX_BKID, JEDEC_XILINX_MFID);
uint32_t result = (manfid | (chip_id & 0xFFFFU));
return (int32_t)(manfid | (chip_id & 0xFFFF)); return (int32_t)result;
} }
int32_t plat_get_soc_revision(void) int32_t plat_get_soc_revision(void)
{ {
return mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET); return (int32_t)mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET);
} }
static uint32_t zynqmp_get_ps_ver(void) static uint32_t zynqmp_get_ps_ver(void)
@ -366,7 +367,7 @@ static void zynqmp_print_platform_name(void)
VERBOSE("TF-A running on %s/%s at 0x%x\n", VERBOSE("TF-A running on %s/%s at 0x%x\n",
zynqmp_print_silicon_idcode(), label, BL31_BASE); zynqmp_print_silicon_idcode(), label, BL31_BASE);
VERBOSE("TF-A running on v%d/RTL%d.%d\n", VERBOSE("TF-A running on v%d/RTL%d.%d\n",
zynqmp_get_ps_ver(), (rtl & 0xf0) >> 4, rtl & 0xf); zynqmp_get_ps_ver(), (rtl & 0xf0U) >> 4U, rtl & 0xfU);
} }
#else #else
static inline void zynqmp_print_platform_name(void) { } static inline void zynqmp_print_platform_name(void) { }
@ -375,7 +376,7 @@ static inline void zynqmp_print_platform_name(void) { }
uint32_t zynqmp_get_bootmode(void) uint32_t zynqmp_get_bootmode(void)
{ {
uint32_t r; uint32_t r;
unsigned int ret; enum pm_ret_status ret;
ret = pm_mmio_read(CRL_APB_BOOT_MODE_USER, &r); ret = pm_mmio_read(CRL_APB_BOOT_MODE_USER, &r);
@ -411,6 +412,6 @@ uint32_t plat_get_syscnt_freq2(void)
if (ver == ZYNQMP_CSU_VERSION_QEMU) { if (ver == ZYNQMP_CSU_VERSION_QEMU) {
return 65000000; return 65000000;
} else { } else {
return mmio_read_32(IOU_SCNTRS_BASEFREQ); return mmio_read_32((uint64_t)IOU_SCNTRS_BASEFREQ);
} }
} }

8
plat/xilinx/zynqmp/bl31_zynqmp_setup.c
View file

@ -59,7 +59,7 @@ static inline void bl31_set_default_config(void)
bl32_image_ep_info.pc = BL32_BASE; bl32_image_ep_info.pc = BL32_BASE;
bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS); DISABLE_ALL_EXCEPTIONS);
} }
@ -96,7 +96,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
tfa_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6); tfa_handoff_addr = (uint64_t)mmio_read_32(PMU_GLOBAL_GEN_STORAGE6);
if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) { if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) {
bl31_set_default_config(); bl31_set_default_config();
@ -109,10 +109,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
panic(); panic();
} }
} }
if (bl32_image_ep_info.pc != 0) { if (bl32_image_ep_info.pc != 0U) {
NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
} }
if (bl33_image_ep_info.pc != 0) { if (bl33_image_ep_info.pc != 0U) {
NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
} }

79
plat/xilinx/zynqmp/include/zynqmp_def.h
View file

@ -60,9 +60,9 @@
/* CRL registers and bitfields */ /* CRL registers and bitfields */
#define CRL_APB_BASE U(0xFF5E0000) #define CRL_APB_BASE U(0xFF5E0000)
#define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200) #define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + U(0x200))
#define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218) #define CRL_APB_RESET_CTRL (CRL_APB_BASE + U(0x218))
#define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + 0x23C) #define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + U(0x23C))
#define CRL_APB_BOOT_PIN_CTRL (CRL_APB_BASE + U(0x250)) #define CRL_APB_BOOT_PIN_CTRL (CRL_APB_BASE + U(0x250))
#define CRL_APB_CLK_BASE U(0xFF5E0020) #define CRL_APB_CLK_BASE U(0xFF5E0020)
@ -75,18 +75,15 @@
#define CRL_APB_BOOT_PIN_MASK (U(0xf0f) << 0) #define CRL_APB_BOOT_PIN_MASK (U(0xf0f) << 0)
#define CRL_APB_BOOT_DRIVE_PIN_1_SHIFT U(9) #define CRL_APB_BOOT_DRIVE_PIN_1_SHIFT U(9)
#define CRL_APB_BOOT_ENABLE_PIN_1_SHIFT U(1) #define CRL_APB_BOOT_ENABLE_PIN_1_SHIFT U(1)
#define CRL_APB_BOOT_ENABLE_PIN_1 (U(0x1) << \ #define CRL_APB_BOOT_ENABLE_PIN_1 (U(0x1) << CRL_APB_BOOT_ENABLE_PIN_1_SHIFT)
CRL_APB_BOOT_ENABLE_PIN_1_SHIFT) #define CRL_APB_BOOT_DRIVE_PIN_1 (U(0x1) << CRL_APB_BOOT_DRIVE_PIN_1_SHIFT)
#define CRL_APB_BOOT_DRIVE_PIN_1 (U(0x1) << \
CRL_APB_BOOT_DRIVE_PIN_1_SHIFT)
#define ZYNQMP_BOOTMODE_JTAG U(0) #define ZYNQMP_BOOTMODE_JTAG U(0)
#define ZYNQMP_ULPI_RESET_VAL_HIGH (CRL_APB_BOOT_ENABLE_PIN_1 | \ #define ZYNQMP_ULPI_RESET_VAL_HIGH (CRL_APB_BOOT_ENABLE_PIN_1 | CRL_APB_BOOT_DRIVE_PIN_1)
CRL_APB_BOOT_DRIVE_PIN_1)
#define ZYNQMP_ULPI_RESET_VAL_LOW CRL_APB_BOOT_ENABLE_PIN_1 #define ZYNQMP_ULPI_RESET_VAL_LOW CRL_APB_BOOT_ENABLE_PIN_1
/* system counter registers and bitfields */ /* system counter registers and bitfields */
#define IOU_SCNTRS_BASE U(0xFF260000) #define IOU_SCNTRS_BASE U(0xFF260000)
#define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + 0x20) #define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + U(0x20))
/* APU registers and bitfields */ /* APU registers and bitfields */
#define APU_BASE U(0xFD5C0000) #define APU_BASE U(0xFD5C0000)
@ -104,11 +101,11 @@
/* PMU registers and bitfields */ /* PMU registers and bitfields */
#define PMU_GLOBAL_BASE U(0xFFD80000) #define PMU_GLOBAL_BASE U(0xFFD80000)
#define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0) #define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0)
#define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + 0x48) #define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + U(0x48))
#define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + 0x110) #define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + U(0x110))
#define PMU_GLOBAL_REQ_PWRUP_EN (PMU_GLOBAL_BASE + 0x118) #define PMU_GLOBAL_REQ_PWRUP_EN (PMU_GLOBAL_BASE + U(0x118))
#define PMU_GLOBAL_REQ_PWRUP_DIS (PMU_GLOBAL_BASE + 0x11c) #define PMU_GLOBAL_REQ_PWRUP_DIS (PMU_GLOBAL_BASE + U(0x11c))
#define PMU_GLOBAL_REQ_PWRUP_TRIG (PMU_GLOBAL_BASE + 0x120) #define PMU_GLOBAL_REQ_PWRUP_TRIG (PMU_GLOBAL_BASE + U(0x120))
#define PMU_GLOBAL_CNTRL_FW_IS_PRESENT (1 << 4) #define PMU_GLOBAL_CNTRL_FW_IS_PRESENT (1 << 4)
@ -191,10 +188,10 @@
#define UART_BAUDRATE 115200 #define UART_BAUDRATE 115200
/* Silicon version detection */ /* Silicon version detection */
#define ZYNQMP_SILICON_VER_MASK 0xF000 #define ZYNQMP_SILICON_VER_MASK U(0xF000)
#define ZYNQMP_SILICON_VER_SHIFT 12 #define ZYNQMP_SILICON_VER_SHIFT 12
#define ZYNQMP_CSU_VERSION_SILICON 0 #define ZYNQMP_CSU_VERSION_SILICON 0
#define ZYNQMP_CSU_VERSION_QEMU 3 #define ZYNQMP_CSU_VERSION_QEMU U(3)
#define ZYNQMP_RTL_VER_MASK 0xFF0U #define ZYNQMP_RTL_VER_MASK 0xFF0U
#define ZYNQMP_RTL_VER_SHIFT 4 #define ZYNQMP_RTL_VER_SHIFT 4
@ -203,38 +200,32 @@
#define ZYNQMP_PS_VER_SHIFT 0 #define ZYNQMP_PS_VER_SHIFT 0
#define ZYNQMP_CSU_BASEADDR U(0xFFCA0000) #define ZYNQMP_CSU_BASEADDR U(0xFFCA0000)
#define ZYNQMP_CSU_IDCODE_OFFSET 0x40U #define ZYNQMP_CSU_IDCODE_OFFSET U(0x40)
#define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT 0U #define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT U(0)
#define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (0xFFFU << \ #define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (U(0xFFF) << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT)
ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT) #define ZYNQMP_CSU_IDCODE_XILINX_ID U(0x093)
#define ZYNQMP_CSU_IDCODE_XILINX_ID 0x093
#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12U #define ZYNQMP_CSU_IDCODE_SVD_SHIFT U(12)
#define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7U << \ #define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7U << ZYNQMP_CSU_IDCODE_SVD_SHIFT)
ZYNQMP_CSU_IDCODE_SVD_SHIFT) #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT U(15)
#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15U #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (U(0xF) << ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xFU << \ #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT U(19)
ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (U(0x3) << ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT)
#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT 19U #define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT U(21)
#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (0x3U << \ #define ZYNQMP_CSU_IDCODE_FAMILY_MASK (U(0x7F) << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT)
ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT) #define ZYNQMP_CSU_IDCODE_FAMILY U(0x23)
#define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT 21U
#define ZYNQMP_CSU_IDCODE_FAMILY_MASK (0x7FU << \
ZYNQMP_CSU_IDCODE_FAMILY_SHIFT)
#define ZYNQMP_CSU_IDCODE_FAMILY 0x23
#define ZYNQMP_CSU_IDCODE_REVISION_SHIFT 28U #define ZYNQMP_CSU_IDCODE_REVISION_SHIFT U(28)
#define ZYNQMP_CSU_IDCODE_REVISION_MASK (0xFU << \ #define ZYNQMP_CSU_IDCODE_REVISION_MASK (U(0xF) << ZYNQMP_CSU_IDCODE_REVISION_SHIFT)
ZYNQMP_CSU_IDCODE_REVISION_SHIFT) #define ZYNQMP_CSU_IDCODE_REVISION U(0)
#define ZYNQMP_CSU_IDCODE_REVISION 0U
#define ZYNQMP_CSU_VERSION_OFFSET 0x44U #define ZYNQMP_CSU_VERSION_OFFSET U(0x44)
/* Efuse */ /* Efuse */
#define EFUSE_BASEADDR U(0xFFCC0000) #define EFUSE_BASEADDR U(0xFFCC0000)
#define EFUSE_IPDISABLE_OFFSET 0x1018 #define EFUSE_IPDISABLE_OFFSET 0x1018
#define EFUSE_IPDISABLE_VERSION 0x1FFU #define EFUSE_IPDISABLE_VERSION U(0x1FF)
#define ZYNQMP_EFUSE_IPDISABLE_SHIFT 20 #define ZYNQMP_EFUSE_IPDISABLE_SHIFT 20
/* Access control register defines */ /* Access control register defines */
@ -356,11 +347,11 @@
#define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300) #define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300)
/* Global general storage register base address */ /* Global general storage register base address */
#define GGS_BASEADDR (0xFFD80030U) #define GGS_BASEADDR U(0xFFD80030)
#define GGS_NUM_REGS U(4) #define GGS_NUM_REGS U(4)
/* Persistent global general storage register base address */ /* Persistent global general storage register base address */
#define PGGS_BASEADDR (0xFFD80050U) #define PGGS_BASEADDR U(0xFFD80050)
#define PGGS_NUM_REGS U(4) #define PGGS_NUM_REGS U(4)
/* PMU GGS4 register 4 is used for warm restart boot health status */ /* PMU GGS4 register 4 is used for warm restart boot health status */
@ -369,7 +360,7 @@
#define PM_BOOT_HEALTH_STATUS_MASK U(0x01) #define PM_BOOT_HEALTH_STATUS_MASK U(0x01)
/* WDT restart scope shift and mask */ /* WDT restart scope shift and mask */
#define RESTART_SCOPE_SHIFT (3) #define RESTART_SCOPE_SHIFT (3)
#define RESTART_SCOPE_MASK (0x3U << RESTART_SCOPE_SHIFT) #define RESTART_SCOPE_MASK (U(0x3) << RESTART_SCOPE_SHIFT)
/* AFI registers */ /* AFI registers */
#define AFIFM6_WRCTRL U(13) #define AFIFM6_WRCTRL U(13)

2
plat/xilinx/zynqmp/plat_psci.c
View file

@ -32,7 +32,7 @@ static void zynqmp_cpu_standby(plat_local_state_t cpu_state)
static int32_t zynqmp_pwr_domain_on(u_register_t mpidr) static int32_t zynqmp_pwr_domain_on(u_register_t mpidr)
{ {
uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); int32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
const struct pm_proc *proc; const struct pm_proc *proc;
uint32_t buff[3]; uint32_t buff[3];
enum pm_ret_status ret; enum pm_ret_status ret;

2
plat/xilinx/zynqmp/plat_zynqmp.c
View file

@ -18,5 +18,5 @@ int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
return -1; return -1;
} }
return zynqmp_calc_core_pos(mpidr); return (int32_t)zynqmp_calc_core_pos(mpidr);
} }

425
plat/xilinx/zynqmp/pm_service/pm_api_clock.c
View file

File diff suppressed because it is too large Load diff

26
plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
View file

@ -266,7 +266,7 @@ static enum pm_ret_status pm_ioctl_sd_set_tapdelay(enum pm_node_id nid,
if (type == PM_TAPDELAY_INPUT) { if (type == PM_TAPDELAY_INPUT) {
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY, ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
(ZYNQMP_SD_ITAPCHGWIN_MASK << shift), (uint64_t)(ZYNQMP_SD_ITAPCHGWIN_MASK << shift),
(ZYNQMP_SD_ITAPCHGWIN << shift)); (ZYNQMP_SD_ITAPCHGWIN << shift));
if (ret != PM_RET_SUCCESS) { if (ret != PM_RET_SUCCESS) {
@ -275,12 +275,12 @@ static enum pm_ret_status pm_ioctl_sd_set_tapdelay(enum pm_node_id nid,
if (value == 0U) { if (value == 0U) {
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY, ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
(ZYNQMP_SD_ITAPDLYENA_MASK << (uint64_t)(ZYNQMP_SD_ITAPDLYENA_MASK <<
shift), 0); shift), 0);
} else { } else {
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY, ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
(ZYNQMP_SD_ITAPDLYENA_MASK << (uint64_t)(ZYNQMP_SD_ITAPDLYENA_MASK <<
shift), (ZYNQMP_SD_ITAPDLYENA << shift), (uint64_t)(ZYNQMP_SD_ITAPDLYENA <<
shift)); shift));
} }
@ -289,7 +289,7 @@ static enum pm_ret_status pm_ioctl_sd_set_tapdelay(enum pm_node_id nid,
} }
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY, ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
(ZYNQMP_SD_ITAPDLYSEL_MASK << shift), (uint64_t)(ZYNQMP_SD_ITAPDLYSEL_MASK << shift),
(value << shift)); (value << shift));
if (ret != PM_RET_SUCCESS) { if (ret != PM_RET_SUCCESS) {
@ -297,17 +297,17 @@ static enum pm_ret_status pm_ioctl_sd_set_tapdelay(enum pm_node_id nid,
} }
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY, ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
(ZYNQMP_SD_ITAPCHGWIN_MASK << shift), 0); (uint64_t)(ZYNQMP_SD_ITAPCHGWIN_MASK << shift), 0);
} else if (type == PM_TAPDELAY_OUTPUT) { } else if (type == PM_TAPDELAY_OUTPUT) {
ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY, ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY,
(ZYNQMP_SD_OTAPDLYENA_MASK << shift), 0); (uint64_t)(ZYNQMP_SD_OTAPDLYENA_MASK << shift), 0);
if (ret != PM_RET_SUCCESS) { if (ret != PM_RET_SUCCESS) {
goto reset_release; goto reset_release;
} }
ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY, ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY,
(ZYNQMP_SD_OTAPDLYSEL_MASK << shift), (uint64_t)(ZYNQMP_SD_OTAPDLYSEL_MASK << shift),
(value << shift)); (value << shift));
} else { } else {
ret = PM_RET_ERROR_ARGS; ret = PM_RET_ERROR_ARGS;
@ -422,7 +422,7 @@ static enum pm_ret_status pm_ioctl_write_ggs(uint32_t index,
return PM_RET_ERROR_ARGS; return PM_RET_ERROR_ARGS;
} }
return pm_mmio_write(GGS_BASEADDR + (index << 2), return pm_mmio_write((uint64_t)(GGS_BASEADDR + (index << 2)),
0xFFFFFFFFU, value); 0xFFFFFFFFU, value);
} }
@ -444,7 +444,7 @@ static enum pm_ret_status pm_ioctl_read_ggs(uint32_t index,
return PM_RET_ERROR_ARGS; return PM_RET_ERROR_ARGS;
} }
return pm_mmio_read(GGS_BASEADDR + (index << 2), value); return pm_mmio_read((uint64_t)(GGS_BASEADDR + (index << 2)), value);
} }
/** /**
@ -465,7 +465,7 @@ static enum pm_ret_status pm_ioctl_write_pggs(uint32_t index,
return PM_RET_ERROR_ARGS; return PM_RET_ERROR_ARGS;
} }
return pm_mmio_write(PGGS_BASEADDR + (index << 2), return pm_mmio_write((uint64_t)(PGGS_BASEADDR + (index << 2)),
0xFFFFFFFFU, value); 0xFFFFFFFFU, value);
} }
@ -530,7 +530,7 @@ static enum pm_ret_status pm_ioctl_read_pggs(uint32_t index,
return PM_RET_ERROR_ARGS; return PM_RET_ERROR_ARGS;
} }
return pm_mmio_read(PGGS_BASEADDR + (index << 2), value); return pm_mmio_read((uint64_t)(PGGS_BASEADDR + (index << 2)), value);
} }
/** /**
@ -703,7 +703,7 @@ enum pm_ret_status tfa_ioctl_bitmask(uint32_t *bit_mask)
IOCTL_AFI, IOCTL_AFI,
}; };
uint8_t i, ioctl_id; uint8_t i, ioctl_id;
int32_t ret; enum pm_ret_status ret;
for (i = 0U; i < ARRAY_SIZE(supported_ids); i++) { for (i = 0U; i < ARRAY_SIZE(supported_ids); i++) {
ioctl_id = supported_ids[i]; ioctl_id = supported_ids[i];

10
plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
View file

@ -1991,7 +1991,7 @@ enum pm_ret_status pm_api_pinctrl_get_num_functions(uint32_t *nfuncs)
enum pm_ret_status pm_api_pinctrl_get_num_func_groups(uint32_t fid, enum pm_ret_status pm_api_pinctrl_get_num_func_groups(uint32_t fid,
uint32_t *ngroups) uint32_t *ngroups)
{ {
if (fid >= MAX_FUNCTION) { if (fid >= (uint32_t)MAX_FUNCTION) {
return PM_RET_ERROR_ARGS; return PM_RET_ERROR_ARGS;
} }
@ -2011,7 +2011,7 @@ enum pm_ret_status pm_api_pinctrl_get_num_func_groups(uint32_t fid,
*/ */
void pm_api_pinctrl_get_function_name(uint32_t fid, char *name) void pm_api_pinctrl_get_function_name(uint32_t fid, char *name)
{ {
if (fid >= MAX_FUNCTION) { if (fid >= (uint32_t)MAX_FUNCTION) {
(void)memcpy(name, END_OF_FUNCTION, FUNCTION_NAME_LEN); (void)memcpy(name, END_OF_FUNCTION, FUNCTION_NAME_LEN);
} else { } else {
(void)memcpy(name, pinctrl_functions[fid].name, FUNCTION_NAME_LEN); (void)memcpy(name, pinctrl_functions[fid].name, FUNCTION_NAME_LEN);
@ -2045,7 +2045,7 @@ enum pm_ret_status pm_api_pinctrl_get_function_groups(uint32_t fid,
uint16_t end_of_grp_offset; uint16_t end_of_grp_offset;
uint16_t i; uint16_t i;
if (fid >= MAX_FUNCTION) { if (fid >= (uint32_t)MAX_FUNCTION) {
return PM_RET_ERROR_ARGS; return PM_RET_ERROR_ARGS;
} }
@ -2058,7 +2058,7 @@ enum pm_ret_status pm_api_pinctrl_get_function_groups(uint32_t fid,
if ((grps + index + i) >= end_of_grp_offset) { if ((grps + index + i) >= end_of_grp_offset) {
break; break;
} }
groups[i] = (grps + index + i); groups[i] = (uint16_t)(grps + index + i);
} }
return PM_RET_SUCCESS; return PM_RET_SUCCESS;
@ -2090,7 +2090,7 @@ enum pm_ret_status pm_api_pinctrl_get_pin_groups(uint32_t pin,
uint32_t i; uint32_t i;
const uint16_t *grps; const uint16_t *grps;
if (pin >= MAX_PIN) { if (pin >= (uint32_t)MAX_PIN) {
return PM_RET_ERROR_ARGS; return PM_RET_ERROR_ARGS;
} }

15
plat/xilinx/zynqmp/pm_service/pm_client.c
View file

@ -46,22 +46,22 @@ static uint32_t suspend_mode = PM_SUSPEND_MODE_STD;
/* Order in pm_procs_all array must match cpu ids */ /* Order in pm_procs_all array must match cpu ids */
static const struct pm_proc pm_procs_all[] = { static const struct pm_proc pm_procs_all[] = {
{ {
.node_id = NODE_APU_0, .node_id = (uint32_t)NODE_APU_0,
.pwrdn_mask = APU_0_PWRCTL_CPUPWRDWNREQ_MASK, .pwrdn_mask = APU_0_PWRCTL_CPUPWRDWNREQ_MASK,
.ipi = &apu_ipi, .ipi = &apu_ipi,
}, },
{ {
.node_id = NODE_APU_1, .node_id = (uint32_t)NODE_APU_1,
.pwrdn_mask = APU_1_PWRCTL_CPUPWRDWNREQ_MASK, .pwrdn_mask = APU_1_PWRCTL_CPUPWRDWNREQ_MASK,
.ipi = &apu_ipi, .ipi = &apu_ipi,
}, },
{ {
.node_id = NODE_APU_2, .node_id = (uint32_t)NODE_APU_2,
.pwrdn_mask = APU_2_PWRCTL_CPUPWRDWNREQ_MASK, .pwrdn_mask = APU_2_PWRCTL_CPUPWRDWNREQ_MASK,
.ipi = &apu_ipi, .ipi = &apu_ipi,
}, },
{ {
.node_id = NODE_APU_3, .node_id = (uint32_t)NODE_APU_3,
.pwrdn_mask = APU_3_PWRCTL_CPUPWRDWNREQ_MASK, .pwrdn_mask = APU_3_PWRCTL_CPUPWRDWNREQ_MASK,
.ipi = &apu_ipi, .ipi = &apu_ipi,
}, },
@ -198,7 +198,7 @@ static void pm_client_set_wakeup_sources(void)
for (reg_num = 0U; reg_num < NUM_GICD_ISENABLER; reg_num++) { for (reg_num = 0U; reg_num < NUM_GICD_ISENABLER; reg_num++) {
uint32_t base_irq = reg_num << ISENABLER_SHIFT; uint32_t base_irq = reg_num << ISENABLER_SHIFT;
uint32_t reg = mmio_read_32(isenabler1 + (reg_num << 2U)); uint32_t reg = mmio_read_32(isenabler1 + (uint64_t)(reg_num << 2U));
if (reg == 0) { if (reg == 0) {
continue; continue;
@ -206,9 +206,10 @@ static void pm_client_set_wakeup_sources(void)
while (reg != 0U) { while (reg != 0U) {
enum pm_node_id node; enum pm_node_id node;
uint32_t idx, ret, irq, lowest_set = reg & (-reg); uint32_t idx, irq, lowest_set = reg & (-reg);
enum pm_ret_status ret;
idx = __builtin_ctz(lowest_set); idx = (uint32_t)__builtin_ctz(lowest_set);
irq = base_irq + idx; irq = base_irq + idx;
if (irq > IRQ_MAX) { if (irq > IRQ_MAX) {

208
plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
View file

@ -51,164 +51,164 @@ typedef struct __attribute__((packed)) {
/* Dependent APIs for TF-A to check their version from firmware */ /* Dependent APIs for TF-A to check their version from firmware */
static const eemi_api_dependency api_dep_table[] = { static const eemi_api_dependency api_dep_table[] = {
{ {
.id = PM_SELF_SUSPEND, .id = (uint8_t)PM_SELF_SUSPEND,
.api_id = PM_SELF_SUSPEND, .api_id = (uint8_t)PM_SELF_SUSPEND,
}, },
{ {
.id = PM_REQ_WAKEUP, .id = (uint8_t)PM_REQ_WAKEUP,
.api_id = PM_REQ_WAKEUP, .api_id = (uint8_t)PM_REQ_WAKEUP,
}, },
{ {
.id = PM_ABORT_SUSPEND, .id = (uint8_t)PM_ABORT_SUSPEND,
.api_id = PM_ABORT_SUSPEND, .api_id = (uint8_t)PM_ABORT_SUSPEND,
}, },
{ {
.id = PM_SET_WAKEUP_SOURCE, .id = (uint8_t)PM_SET_WAKEUP_SOURCE,
.api_id = PM_SET_WAKEUP_SOURCE, .api_id = (uint8_t)PM_SET_WAKEUP_SOURCE,
}, },
{ {
.id = PM_SYSTEM_SHUTDOWN, .id = (uint8_t)PM_SYSTEM_SHUTDOWN,
.api_id = PM_SYSTEM_SHUTDOWN, .api_id = (uint8_t)PM_SYSTEM_SHUTDOWN,
}, },
{ {
.id = PM_GET_API_VERSION, .id = (uint8_t)PM_GET_API_VERSION,
.api_id = PM_GET_API_VERSION, .api_id = (uint8_t)PM_GET_API_VERSION,
}, },
{ {
.id = PM_CLOCK_ENABLE, .id = (uint8_t)PM_CLOCK_ENABLE,
.api_id = PM_PLL_SET_MODE, .api_id = (uint8_t)PM_PLL_SET_MODE,
}, },
{ {
.id = PM_CLOCK_ENABLE, .id = (uint8_t)PM_CLOCK_ENABLE,
.api_id = PM_CLOCK_ENABLE, .api_id = (uint8_t)PM_CLOCK_ENABLE,
}, },
{ {
.id = PM_CLOCK_DISABLE, .id = (uint8_t)PM_CLOCK_DISABLE,
.api_id = PM_PLL_SET_MODE, .api_id = (uint8_t)PM_PLL_SET_MODE,
}, },
{ {
.id = PM_CLOCK_DISABLE, .id = (uint8_t)PM_CLOCK_DISABLE,
.api_id = PM_CLOCK_DISABLE, .api_id = (uint8_t)PM_CLOCK_DISABLE,
}, },
{ {
.id = PM_CLOCK_GETSTATE, .id = (uint8_t)PM_CLOCK_GETSTATE,
.api_id = PM_PLL_GET_MODE, .api_id = (uint8_t)PM_PLL_GET_MODE,
}, },
{ {
.id = PM_CLOCK_GETSTATE, .id = (uint8_t)PM_CLOCK_GETSTATE,
.api_id = PM_CLOCK_GETSTATE, .api_id = (uint8_t)PM_CLOCK_GETSTATE,
}, },
{ {
.id = PM_CLOCK_SETDIVIDER, .id = (uint8_t)PM_CLOCK_SETDIVIDER,
.api_id = PM_PLL_SET_PARAMETER, .api_id = (uint8_t)PM_PLL_SET_PARAMETER,
}, },
{ {
.id = PM_CLOCK_SETDIVIDER, .id = (uint8_t)PM_CLOCK_SETDIVIDER,
.api_id = PM_CLOCK_SETDIVIDER, .api_id = (uint8_t)PM_CLOCK_SETDIVIDER,
}, },
{ {
.id = PM_CLOCK_GETDIVIDER, .id = (uint8_t)PM_CLOCK_GETDIVIDER,
.api_id = PM_PLL_GET_PARAMETER, .api_id = (uint8_t)PM_PLL_GET_PARAMETER,
}, },
{ {
.id = PM_CLOCK_GETDIVIDER, .id = (uint8_t)PM_CLOCK_GETDIVIDER,
.api_id = PM_CLOCK_GETDIVIDER, .api_id = (uint8_t)PM_CLOCK_GETDIVIDER,
}, },
{ {
.id = PM_CLOCK_SETPARENT, .id = (uint8_t)PM_CLOCK_SETPARENT,
.api_id = PM_PLL_SET_PARAMETER, .api_id = (uint8_t)PM_PLL_SET_PARAMETER,
}, },
{ {
.id = PM_CLOCK_SETPARENT, .id = (uint8_t)PM_CLOCK_SETPARENT,
.api_id = PM_CLOCK_SETPARENT, .api_id = (uint8_t)PM_CLOCK_SETPARENT,
}, },
{ {
.id = PM_CLOCK_GETPARENT, .id = (uint8_t)PM_CLOCK_GETPARENT,
.api_id = PM_PLL_GET_PARAMETER, .api_id = (uint8_t)PM_PLL_GET_PARAMETER,
}, },
{ {
.id = PM_CLOCK_GETPARENT, .id = (uint8_t)PM_CLOCK_GETPARENT,
.api_id = PM_CLOCK_GETPARENT, .api_id = (uint8_t)PM_CLOCK_GETPARENT,
}, },
{ {
.id = PM_PLL_SET_PARAMETER, .id = (uint8_t)PM_PLL_SET_PARAMETER,
.api_id = PM_PLL_SET_PARAMETER, .api_id = (uint8_t)PM_PLL_SET_PARAMETER,
}, },
{ {
.id = PM_PLL_GET_PARAMETER, .id = (uint8_t)PM_PLL_GET_PARAMETER,
.api_id = PM_PLL_GET_PARAMETER, .api_id = (uint8_t)PM_PLL_GET_PARAMETER,
}, },
{ {
.id = PM_PLL_SET_MODE, .id = (uint8_t)PM_PLL_SET_MODE,
.api_id = PM_PLL_SET_MODE, .api_id = (uint8_t)PM_PLL_SET_MODE,
}, },
{ {
.id = PM_PLL_GET_MODE, .id = (uint8_t)PM_PLL_GET_MODE,
.api_id = PM_PLL_GET_MODE, .api_id = (uint8_t)PM_PLL_GET_MODE,
}, },
{ {
.id = PM_REGISTER_ACCESS, .id = (uint8_t)PM_REGISTER_ACCESS,
.api_id = PM_MMIO_WRITE, .api_id = (uint8_t)PM_MMIO_WRITE,
}, },
{ {
.id = PM_REGISTER_ACCESS, .id = (uint8_t)PM_REGISTER_ACCESS,
.api_id = PM_MMIO_READ, .api_id = (uint8_t)PM_MMIO_READ,
}, },
{ {
.id = PM_FEATURE_CHECK, .id = (uint8_t)PM_FEATURE_CHECK,
.api_id = PM_FEATURE_CHECK, .api_id = (uint8_t)PM_FEATURE_CHECK,
}, },
{ {
.id = IOCTL_SET_TAPDELAY_BYPASS, .id = (uint8_t)IOCTL_SET_TAPDELAY_BYPASS,
.api_id = PM_MMIO_WRITE, .api_id = (uint8_t)PM_MMIO_WRITE,
}, },
{ {
.id = IOCTL_SD_DLL_RESET, .id = (uint8_t)IOCTL_SD_DLL_RESET,
.api_id = PM_MMIO_WRITE, .api_id = (uint8_t)PM_MMIO_WRITE,
}, },
{ {
.id = IOCTL_SET_SD_TAPDELAY, .id = (uint8_t)IOCTL_SET_SD_TAPDELAY,
.api_id = PM_MMIO_WRITE, .api_id = (uint8_t)PM_MMIO_WRITE,
}, },
{ {
.id = IOCTL_SET_SD_TAPDELAY, .id = (uint8_t)IOCTL_SET_SD_TAPDELAY,
.api_id = PM_MMIO_READ, .api_id = (uint8_t)PM_MMIO_READ,
}, },
{ {
.id = IOCTL_SET_PLL_FRAC_DATA, .id = (uint8_t)IOCTL_SET_PLL_FRAC_DATA,
.api_id = PM_PLL_SET_PARAMETER, .api_id = (uint8_t)PM_PLL_SET_PARAMETER,
}, },
{ {
.id = IOCTL_GET_PLL_FRAC_DATA, .id = (uint8_t)IOCTL_GET_PLL_FRAC_DATA,
.api_id = PM_PLL_GET_PARAMETER, .api_id = (uint8_t)PM_PLL_GET_PARAMETER,
}, },
{ {
.id = IOCTL_WRITE_GGS, .id = (uint8_t)IOCTL_WRITE_GGS,
.api_id = PM_MMIO_WRITE, .api_id = (uint8_t)PM_MMIO_WRITE,
}, },
{ {
.id = IOCTL_READ_GGS, .id = (uint8_t)IOCTL_READ_GGS,
.api_id = PM_MMIO_READ, .api_id = (uint8_t)PM_MMIO_READ,
}, },
{ {
.id = IOCTL_WRITE_PGGS, .id = (uint8_t)IOCTL_WRITE_PGGS,
.api_id = PM_MMIO_WRITE, .api_id = (uint8_t)PM_MMIO_WRITE,
}, },
{ {
.id = IOCTL_READ_PGGS, .id = (uint8_t)IOCTL_READ_PGGS,
.api_id = PM_MMIO_READ, .api_id = (uint8_t)PM_MMIO_READ,
}, },
{ {
.id = IOCTL_ULPI_RESET, .id = (uint8_t)IOCTL_ULPI_RESET,
.api_id = PM_MMIO_WRITE, .api_id = (uint8_t)PM_MMIO_WRITE,
}, },
{ {
.id = IOCTL_SET_BOOT_HEALTH_STATUS, .id = (uint8_t)IOCTL_SET_BOOT_HEALTH_STATUS,
.api_id = PM_MMIO_WRITE, .api_id = (uint8_t)PM_MMIO_WRITE,
}, },
{ {
.id = IOCTL_AFI, .id = (uint8_t)IOCTL_AFI,
.api_id = PM_MMIO_WRITE, .api_id = (uint8_t)PM_MMIO_WRITE,
}, },
}; };
@ -343,7 +343,7 @@ enum pm_ret_status pm_req_wakeup(enum pm_node_id target,
/* encode set Address into 1st bit of address */ /* encode set Address into 1st bit of address */
encoded_address = address; encoded_address = address;
encoded_address |= !!set_address; encoded_address |= (uint32_t)!!set_address;
/* Send request to the PMU to perform the wake of the PU */ /* Send request to the PMU to perform the wake of the PU */
PM_PACK_PAYLOAD5(payload, PM_REQ_WAKEUP, target, encoded_address, PM_PACK_PAYLOAD5(payload, PM_REQ_WAKEUP, target, encoded_address,
@ -440,7 +440,7 @@ enum pm_ret_status pm_system_shutdown(uint32_t type, uint32_t subtype)
{ {
uint32_t payload[PAYLOAD_ARG_CNT]; uint32_t payload[PAYLOAD_ARG_CNT];
if (type == PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY) { if (type == (uint32_t)PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY) {
/* Setting scope for subsequent PSCI reboot or shutdown */ /* Setting scope for subsequent PSCI reboot or shutdown */
pm_shutdown_scope = subtype; pm_shutdown_scope = subtype;
return PM_RET_SUCCESS; return PM_RET_SUCCESS;
@ -710,7 +710,7 @@ enum pm_ret_status pm_get_callbackdata(uint32_t *data, size_t count)
{ {
enum pm_ret_status ret = PM_RET_SUCCESS; enum pm_ret_status ret = PM_RET_SUCCESS;
/* Return if interrupt is not from PMU */ /* Return if interrupt is not from PMU */
if (!pm_ipi_irq_status(primary_proc)) { if ((pm_ipi_irq_status(primary_proc) == 0U)) {
return ret; return ret;
} }
@ -770,7 +770,7 @@ enum pm_ret_status check_api_dependency(uint8_t id)
{ {
uint8_t i; uint8_t i;
uint32_t version_type; uint32_t version_type;
int ret; enum pm_ret_status ret;
for (i = 0U; i < ARRAY_SIZE(api_dep_table); i++) { for (i = 0U; i < ARRAY_SIZE(api_dep_table); i++) {
if (api_dep_table[i].id == id) { if (api_dep_table[i].id == id) {
@ -780,7 +780,7 @@ enum pm_ret_status check_api_dependency(uint8_t id)
ret = fw_api_version(api_dep_table[i].api_id, ret = fw_api_version(api_dep_table[i].api_id,
&version_type, 1); &version_type, 1);
if (ret != PM_RET_SUCCESS) { if (ret != (uint32_t)PM_RET_SUCCESS) {
return ret; return ret;
} }
@ -898,7 +898,7 @@ static enum pm_ret_status feature_check_partial(uint32_t api_id,
case PM_REGISTER_ACCESS: case PM_REGISTER_ACCESS:
case PM_FEATURE_CHECK: case PM_FEATURE_CHECK:
status = check_api_dependency(api_id); status = check_api_dependency(api_id);
if (status != PM_RET_SUCCESS) { if (status != (uint32_t)PM_RET_SUCCESS) {
return status; return status;
} }
return get_tfa_version_for_partial_apis(api_id, version); return get_tfa_version_for_partial_apis(api_id, version);
@ -925,13 +925,13 @@ enum pm_ret_status pm_feature_check(uint32_t api_id, uint32_t *version,
/* Get API version implemented in TF-A */ /* Get API version implemented in TF-A */
status = feature_check_tfa(api_id, version, bit_mask); status = feature_check_tfa(api_id, version, bit_mask);
if (status != PM_RET_ERROR_NO_FEATURE) { if (status != (uint32_t)PM_RET_ERROR_NO_FEATURE) {
return status; return status;
} }
/* Get API version implemented by firmware and TF-A both */ /* Get API version implemented by firmware and TF-A both */
status = feature_check_partial(api_id, version); status = feature_check_partial(api_id, version);
if (status != PM_RET_ERROR_NO_FEATURE) { if (status != (uint32_t)PM_RET_ERROR_NO_FEATURE) {
return status; return status;
} }
@ -940,20 +940,20 @@ enum pm_ret_status pm_feature_check(uint32_t api_id, uint32_t *version,
/* IOCTL call may return failure whose ID is not implemented in /* IOCTL call may return failure whose ID is not implemented in
* firmware but implemented in TF-A * firmware but implemented in TF-A
*/ */
if ((api_id != PM_IOCTL) && (status != PM_RET_SUCCESS)) { if ((api_id != (uint32_t)PM_IOCTL) && (status != PM_RET_SUCCESS)) {
return status; return status;
} }
*version = ret_payload[0]; *version = ret_payload[0];
/* Update IOCTL bit mask which are implemented in TF-A */ /* Update IOCTL bit mask which are implemented in TF-A */
if ((api_id == PM_IOCTL) || (api_id == PM_GET_OP_CHARACTERISTIC)) { if ((api_id == (uint32_t)PM_IOCTL) || (api_id == (uint32_t)PM_GET_OP_CHARACTERISTIC)) {
if (len < 2) { if (len < 2U) {
return PM_RET_ERROR_ARGS; return PM_RET_ERROR_ARGS;
} }
bit_mask[0] = ret_payload[1]; bit_mask[0] = ret_payload[1];
bit_mask[1] = ret_payload[2]; bit_mask[1] = ret_payload[2];
if (api_id == PM_IOCTL) { if (api_id == (uint32_t)PM_IOCTL) {
/* Get IOCTL's implemented by TF-A */ /* Get IOCTL's implemented by TF-A */
status = tfa_ioctl_bitmask(bit_mask); status = tfa_ioctl_bitmask(bit_mask);
} }
@ -1521,47 +1521,47 @@ void pm_query_data(enum pm_query_ids qid, uint32_t arg1, uint32_t arg2,
pm_clock_get_name(arg1, (char *)data); pm_clock_get_name(arg1, (char *)data);
break; break;
case PM_QID_CLOCK_GET_TOPOLOGY: case PM_QID_CLOCK_GET_TOPOLOGY:
data[0] = pm_clock_get_topology(arg1, arg2, &data[1]); data[0] = (uint32_t)pm_clock_get_topology(arg1, arg2, &data[1]);
break; break;
case PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS: case PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS:
data[0] = pm_clock_get_fixedfactor_params(arg1, &data[1], data[0] = (uint32_t)pm_clock_get_fixedfactor_params(arg1, &data[1],
&data[2]); &data[2]);
break; break;
case PM_QID_CLOCK_GET_PARENTS: case PM_QID_CLOCK_GET_PARENTS:
data[0] = pm_clock_get_parents(arg1, arg2, &data[1]); data[0] = (uint32_t)pm_clock_get_parents(arg1, arg2, &data[1]);
break; break;
case PM_QID_CLOCK_GET_ATTRIBUTES: case PM_QID_CLOCK_GET_ATTRIBUTES:
data[0] = pm_clock_get_attributes(arg1, &data[1]); data[0] = (uint32_t)pm_clock_get_attributes(arg1, &data[1]);
break; break;
case PM_QID_PINCTRL_GET_NUM_PINS: case PM_QID_PINCTRL_GET_NUM_PINS:
data[0] = pm_pinctrl_get_num_pins(&data[1]); data[0] = (uint32_t)pm_pinctrl_get_num_pins(&data[1]);
break; break;
case PM_QID_PINCTRL_GET_NUM_FUNCTIONS: case PM_QID_PINCTRL_GET_NUM_FUNCTIONS:
data[0] = pm_pinctrl_get_num_functions(&data[1]); data[0] = (uint32_t)pm_pinctrl_get_num_functions(&data[1]);
break; break;
case PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS: case PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS:
data[0] = pm_pinctrl_get_num_function_groups(arg1, &data[1]); data[0] = (uint32_t)pm_pinctrl_get_num_function_groups(arg1, &data[1]);
break; break;
case PM_QID_PINCTRL_GET_FUNCTION_NAME: case PM_QID_PINCTRL_GET_FUNCTION_NAME:
pm_pinctrl_get_function_name(arg1, (char *)data); pm_pinctrl_get_function_name(arg1, (char *)data);
break; break;
case PM_QID_PINCTRL_GET_FUNCTION_GROUPS: case PM_QID_PINCTRL_GET_FUNCTION_GROUPS:
data[0] = pm_pinctrl_get_function_groups(arg1, arg2, data[0] = (uint32_t)pm_pinctrl_get_function_groups(arg1, arg2,
(uint16_t *)&data[1]); (uint16_t *)&data[1]);
break; break;
case PM_QID_PINCTRL_GET_PIN_GROUPS: case PM_QID_PINCTRL_GET_PIN_GROUPS:
data[0] = pm_pinctrl_get_pin_groups(arg1, arg2, data[0] = (uint32_t)pm_pinctrl_get_pin_groups(arg1, arg2,
(uint16_t *)&data[1]); (uint16_t *)&data[1]);
break; break;
case PM_QID_CLOCK_GET_NUM_CLOCKS: case PM_QID_CLOCK_GET_NUM_CLOCKS:
data[0] = pm_clock_get_num_clocks(&data[1]); data[0] = (uint32_t)pm_clock_get_num_clocks(&data[1]);
break; break;
case PM_QID_CLOCK_GET_MAX_DIVISOR: case PM_QID_CLOCK_GET_MAX_DIVISOR:
data[0] = pm_clock_get_max_divisor(arg1, arg2, &data[1]); data[0] = (uint32_t)pm_clock_get_max_divisor(arg1, (uint8_t)arg2, &data[1]);
break; break;
default: default:
data[0] = PM_RET_ERROR_ARGS; data[0] = (uint32_t)PM_RET_ERROR_ARGS;
WARN("Unimplemented query service call: 0x%x\n", qid); WARN("Unimplemented query service call: 0x%x\n", qid);
break; break;
} }

6
plat/xilinx/zynqmp/pm_service/zynqmp_pm_defs.h
View file

@ -187,9 +187,9 @@ enum pm_shutdown_type {
* *
*/ */
enum pm_shutdown_subtype { enum pm_shutdown_subtype {
PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM, PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM = (0U),
PMF_SHUTDOWN_SUBTYPE_PS_ONLY, PMF_SHUTDOWN_SUBTYPE_PS_ONLY = (1U),
PMF_SHUTDOWN_SUBTYPE_SYSTEM, PMF_SHUTDOWN_SUBTYPE_SYSTEM = (2U),
}; };
/** /**

8
plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
View file

@ -253,7 +253,7 @@ int32_t pm_setup(void)
ret = status; ret = status;
} }
pm_up = !status; pm_up = (status == 0);
return ret; return ret;
} }
@ -322,7 +322,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
uint32_t set_addr = pm_arg[1] & 0x1U; uint32_t set_addr = pm_arg[1] & 0x1U;
uint64_t address = (uint64_t)pm_arg[2] << 32U; uint64_t address = (uint64_t)pm_arg[2] << 32U;
address |= pm_arg[1] & (~0x1U); address |= (uint64_t)(pm_arg[1] & (~0x1U));
ret = pm_req_wakeup(pm_arg[0], set_addr, address, ret = pm_req_wakeup(pm_arg[0], set_addr, address,
pm_arg[3]); pm_arg[3]);
SMC_RET1(handle, (uint64_t)ret); SMC_RET1(handle, (uint64_t)ret);
@ -354,7 +354,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
SMC_RET1(handle, (uint64_t)ret); SMC_RET1(handle, (uint64_t)ret);
case PM_GET_API_VERSION: case PM_GET_API_VERSION:
if (ipi_irq_flag == 0U) { if ((uint32_t)ipi_irq_flag == 0U) {
/* /*
* Enable IPI IRQ * Enable IPI IRQ
* assume the rich OS is OK to handle callback IRQs now. * assume the rich OS is OK to handle callback IRQs now.
@ -560,7 +560,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
uint32_t bit_mask[2] = {0}; uint32_t bit_mask[2] = {0};
ret = pm_feature_check(pm_arg[0], &version_type, bit_mask, ret = pm_feature_check(pm_arg[0], &version_type, bit_mask,
ARRAY_SIZE(bit_mask)); (uint8_t)ARRAY_SIZE(bit_mask));
SMC_RET2(handle, ((uint64_t)ret | ((uint64_t)version_type << 32U)), SMC_RET2(handle, ((uint64_t)ret | ((uint64_t)version_type << 32U)),
((uint64_t)bit_mask[0] | ((uint64_t)bit_mask[1] << 32U))); ((uint64_t)bit_mask[0] | ((uint64_t)bit_mask[1] << 32U)));
} }