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Workaround for Neoverse N1 erratum 1220197

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Neoverse N1 erratum 1220197 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set two bits in the implementation defined
CPUECTLR_EL1 system register, which disables write streaming to the L2.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
This commit is contained in:
lauwal01 2019-06-24 11:38:53 -05:00
parent ef5fa7d477
commit 9eceb020d7
4 changed files with 46 additions and 0 deletions
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3
docs/design/cpu-specific-build-macros.rst
View file

@ -240,6 +240,9 @@ For Neoverse N1, the following errata build flags are defined :
- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1
CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1
CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1
CPU. This needs to be enabled only for revision <= r3p0 of the CPU.

2
include/lib/cpus/aarch64/neoverse_n1.h
View file

@ -30,6 +30,8 @@
******************************************************************************/
#define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4
#define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/

33
lib/cpus/aarch64/neoverse_n1.S
View file

@ -184,6 +184,33 @@ func check_errata_1207823
b cpu_rev_var_ls
endfunc check_errata_1207823
/* --------------------------------------------------
* Errata Workaround for Neoverse N1 Errata #1220197
* This applies to revision <=r2p0 of Neoverse N1.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_n1_1220197_wa
/* Compare x0 against revision r2p0 */
mov x17, x30
bl check_errata_1220197
cbz x0, 1f
mrs x1, NEOVERSE_N1_CPUECTLR_EL1
orr x1, x1, NEOVERSE_N1_WS_THR_L2_MASK
msr NEOVERSE_N1_CPUECTLR_EL1, x1
isb
1:
ret x17
endfunc errata_n1_1220197_wa
func check_errata_1220197
/* Applies to <=r2p0 */
mov x1, #0x20
b cpu_rev_var_ls
endfunc check_errata_1220197
/* --------------------------------------------------
* Errata Workaround for Neoverse N1 Erratum 1315703.
* This applies to revision <= r3p0 of Neoverse N1.
@ -252,6 +279,11 @@ func neoverse_n1_reset_func
bl errata_n1_1207823_wa
#endif
#if ERRATA_N1_1220197
mov x0, x18
bl errata_n1_1220197_wa
#endif
#if ERRATA_N1_1315703
mov x0, x18
bl errata_n1_1315703_wa
@ -318,6 +350,7 @@ func neoverse_n1_errata_report
report_errata ERRATA_N1_1130799, neoverse_n1, 1130799
report_errata ERRATA_N1_1165347, neoverse_n1, 1165347
report_errata ERRATA_N1_1207823, neoverse_n1, 1207823
report_errata ERRATA_N1_1220197, neoverse_n1, 1220197
report_errata ERRATA_N1_1315703, neoverse_n1, 1315703
report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184

8
lib/cpus/cpu-ops.mk
View file

@ -254,6 +254,10 @@ ERRATA_N1_1165347 ?=0
# only to revision <= r2p0 of the Neoverse N1 cpu.
ERRATA_N1_1207823 ?=0
# Flag to apply erratum 1220197 workaround during reset. This erratum applies
# only to revision <= r2p0 of the Neoverse N1 cpu.
ERRATA_N1_1220197 ?=0
# Flag to apply erratum 1315703 workaround during reset. This erratum applies
# to revisions before r3p1 of the Neoverse N1 cpu.
ERRATA_N1_1315703 ?=1
@ -463,6 +467,10 @@ $(eval $(call add_define,ERRATA_N1_1165347))
$(eval $(call assert_boolean,ERRATA_N1_1207823))
$(eval $(call add_define,ERRATA_N1_1207823))
# Process ERRATA_N1_1220197 flag
$(eval $(call assert_boolean,ERRATA_N1_1220197))
$(eval $(call add_define,ERRATA_N1_1220197))
# Process ERRATA_N1_1315703 flag
$(eval $(call assert_boolean,ERRATA_N1_1315703))
$(eval $(call add_define,ERRATA_N1_1315703))