Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-17 10:04:26 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

feat(ls1088a): add new SoC platform ls1088a

Browse source 
LS1088A is a cost-effective, powerefficient, and highly integrated
SoC device featuring eight extremely power-efficient 64-bit ARM
Cortex-A53 cores with ECC-protected L1 and L2 cache memories for
high reliability, running up to 1.6 GHz.

This patch is to add ls1088a SoC support in TF-A.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Id9ebcdad1beab07ea81a41955edd4f471d6cf090
This commit is contained in:
Jiafei Pan 2022-02-18 15:26:08 +08:00
parent ccb71e33eb
commit 9df5ba05b4
7 changed files with 2710 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
plat/nxp/common/setup/ls_bl2_el3_setup.c
View file

@ -182,7 +182,7 @@ void ls_bl2_el3_plat_arch_setup(void)
unsigned int flags = 0U;
/* Initialise the IO layer and register platform IO devices */
ls_setup_page_tables(
#if SEPARATE_RW_AND_NOLOAD
#if SEPARATE_BL2_NOLOAD_REGION
BL2_START,
BL2_LIMIT - BL2_START,
#else

1817
plat/nxp/soc-ls1088a/aarch64/ls1088a.S Normal file
View file

File diff suppressed because it is too large Load diff

69
plat/nxp/soc-ls1088a/aarch64/ls1088a_helpers.S Normal file
View file

@ -0,0 +1,69 @@
/*
* Copyright 2022 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <platform_def.h>
.globl plat_secondary_cold_boot_setup
.globl plat_is_my_cpu_primary
.globl plat_reset_handler
.globl platform_mem_init
func platform_mem1_init
ret
endfunc platform_mem1_init
func platform_mem_init
ret
endfunc platform_mem_init
func apply_platform_errata
ret
endfunc apply_platform_errata
func plat_reset_handler
mov x29, x30
bl apply_platform_errata
#if defined(IMAGE_BL31)
ldr x0, =POLICY_SMMU_PAGESZ_64K
cbz x0, 1f
/* Set the SMMU page size in the sACR register */
bl _set_smmu_pagesz_64
#endif
1:
mov x30, x29
ret
endfunc plat_reset_handler
/*
* void plat_secondary_cold_boot_setup (void);
*
* This function performs any platform specific actions
* needed for a secondary cpu after a cold reset e.g
* mark the cpu's presence, mechanism to place it in a
* holding pen etc.
*/
func plat_secondary_cold_boot_setup
/* ls1088a does not do cold boot for secondary CPU */
cb_panic:
b cb_panic
endfunc plat_secondary_cold_boot_setup
/*
* unsigned int plat_is_my_cpu_primary (void);
*
* Find out whether the current cpu is the primary
* cpu.
*/
func plat_is_my_cpu_primary
mrs x0, mpidr_el1
and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
cmp x0, 0x0
cset w0, eq
ret
endfunc plat_is_my_cpu_primary

229
plat/nxp/soc-ls1088a/include/soc.h Normal file
View file

@ -0,0 +1,229 @@
/*
* Copyright 2022 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SOC_H
#define SOC_H
/* Chassis specific defines - common across SoC's of a particular platform */
#include "dcfg_lsch3.h"
#include "soc_default_base_addr.h"
#include "soc_default_helper_macros.h"
/*
* SVR Definition of LS1088A
* A: without security
* AE: with security
* (not include major and minor rev)
*/
#define SVR_LS1044A 0x870323
#define SVR_LS1044AE 0x870322
#define SVR_LS1048A 0x870321
#define SVR_LS1048AE 0x870320
#define SVR_LS1084A 0x870303
#define SVR_LS1084AE 0x870302
#define SVR_LS1088A 0x870301
#define SVR_LS1088AE 0x870300
#define SVR_WO_E 0xFFFFFE
/* Number of cores in platform */
#define NUMBER_OF_CLUSTERS 2
#define CORES_PER_CLUSTER 4
#define PLATFORM_CORE_COUNT (NUMBER_OF_CLUSTERS * CORES_PER_CLUSTER)
/* set to 0 if the clusters are not symmetrical */
#define SYMMETRICAL_CLUSTERS 1
#define NUM_DRAM_REGIONS 2
#define NXP_DRAM0_ADDR 0x80000000
#define NXP_DRAM0_MAX_SIZE 0x80000000 /* 2 GB */
#define NXP_DRAM1_ADDR 0x8080000000
#define NXP_DRAM1_MAX_SIZE 0x7F80000000 /* 510 G */
/* DRAM0 Size defined in platform_def.h */
#define NXP_DRAM0_SIZE PLAT_DEF_DRAM0_SIZE
#define NXP_POWMGTDCR 0x700123C20
/* epu register offsets and values */
#define EPU_EPGCR_OFFSET 0x0
#define EPU_EPIMCR10_OFFSET 0x128
#define EPU_EPCTR10_OFFSET 0xa28
#define EPU_EPCCR10_OFFSET 0x828
#ifdef EPU_EPCCR10_VAL
#undef EPU_EPCCR10_VAL
#endif
#define EPU_EPCCR10_VAL 0xf2800000
#define EPU_EPIMCR10_VAL 0xba000000
#define EPU_EPCTR10_VAL 0x0
#define EPU_EPGCR_VAL (1 << 31)
/* pmu register offsets and values */
#define PMU_PCPW20SR_OFFSET 0x830
#define PMU_CLAINACTSETR_OFFSET 0x1100
#define PMU_CLAINACTCLRR_OFFSET 0x1104
#define PMU_CLSINACTSETR_OFFSET 0x1108
#define PMU_CLSINACTCLRR_OFFSET 0x110C
#define PMU_CLL2FLUSHSETR_OFFSET 0x1110
#define PMU_CLSL2FLUSHCLRR_OFFSET 0x1114
#define PMU_CLL2FLUSHSR_OFFSET 0x1118
#define PMU_POWMGTCSR_OFFSET 0x4000
#define PMU_IPPDEXPCR0_OFFSET 0x4040
#define PMU_IPPDEXPCR1_OFFSET 0x4044
#define PMU_IPPDEXPCR2_OFFSET 0x4048
#define PMU_IPPDEXPCR3_OFFSET 0x404C
#define PMU_IPPDEXPCR4_OFFSET 0x4050
#define PMU_IPPDEXPCR5_OFFSET 0x4054
#define PMU_IPSTPCR0_OFFSET 0x4120
#define PMU_IPSTPCR1_OFFSET 0x4124
#define PMU_IPSTPCR2_OFFSET 0x4128
#define PMU_IPSTPCR3_OFFSET 0x412C
#define PMU_IPSTPCR4_OFFSET 0x4130
#define PMU_IPSTPCR5_OFFSET 0x4134
#define PMU_IPSTPCR6_OFFSET 0x4138
#define PMU_IPSTPACK0_OFFSET 0x4140
#define PMU_IPSTPACK1_OFFSET 0x4144
#define PMU_IPSTPACK2_OFFSET 0x4148
#define PMU_IPSTPACK3_OFFSET 0x414C
#define PMU_IPSTPACK4_OFFSET 0x4150
#define PMU_IPSTPACK5_OFFSET 0x4154
#define PMU_IPSTPACK6_OFFSET 0x4158
#define PMU_POWMGTCSR_VAL (1 << 20)
#define IPPDEXPCR0_MASK 0xFFFFFFFF
#define IPPDEXPCR1_MASK 0xFFFFFFFF
#define IPPDEXPCR2_MASK 0xFFFFFFFF
#define IPPDEXPCR3_MASK 0xFFFFFFFF
#define IPPDEXPCR4_MASK 0xFFFFFFFF
#define IPPDEXPCR5_MASK 0xFFFFFFFF
/* DEVDISR5_FLX_TMR */
#define IPPDEXPCR_FLX_TMR 0x00004000
#define DEVDISR5_FLX_TMR 0x00004000
#define IPSTPCR0_VALUE 0x0041310C
#define IPSTPCR1_VALUE 0x000003FF
#define IPSTPCR2_VALUE 0x00013006
/* Dont' stop UART */
#define IPSTPCR3_VALUE 0x0000033A
#define IPSTPCR4_VALUE 0x00103300
#define IPSTPCR5_VALUE 0x00000001
#define IPSTPCR6_VALUE 0x00000000
#define TZPC_BLOCK_SIZE 0x1000
/* PORSR1 */
#define PORSR1_RCW_MASK 0xFF800000
#define PORSR1_RCW_SHIFT 23
/* CFG_RCW_SRC[6:0] */
#define RCW_SRC_TYPE_MASK 0x70
/* RCW SRC NOR */
#define NOR_16B_VAL 0x20
/*
* RCW SRC Serial Flash
* 1. SERAIL NOR (QSPI)
* 2. OTHERS (SD/MMC, SPI, I2C1)
*/
#define RCW_SRC_SERIAL_MASK 0x7F
#define QSPI_VAL 0x62
#define SDHC_VAL 0x40
#define EMMC_VAL 0x41
/*
* Required LS standard platform porting definitions
* for CCN-504 - Read from RN-F node ID register
*/
#define PLAT_CLUSTER_TO_CCN_ID_MAP 1, 9, 11, 19
/* Defines required for using XLAT tables from ARM common code */
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 40)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 40)
/*
* Clock Divisors
*/
#define NXP_PLATFORM_CLK_DIVIDER 1
#define NXP_UART_CLK_DIVIDER 2
/* dcfg register offsets and values */
#define DCFG_DEVDISR1_OFFSET 0x70
#define DCFG_DEVDISR2_OFFSET 0x74
#define DCFG_DEVDISR3_OFFSET 0x78
#define DCFG_DEVDISR5_OFFSET 0x80
#define DCFG_DEVDISR6_OFFSET 0x84
#define DCFG_DEVDISR1_SEC (1 << 22)
#define DCFG_DEVDISR3_QBMAIN (1 << 12)
#define DCFG_DEVDISR4_SPI_QSPI (1 << 4 | 1 << 5)
#define DCFG_DEVDISR5_MEM (1 << 0)
#define DEVDISR1_VALUE 0x0041310c
#define DEVDISR2_VALUE 0x000003ff
#define DEVDISR3_VALUE 0x00013006
#define DEVDISR4_VALUE 0x0000033e
#define DEVDISR5_VALUE 0x00103300
#define DEVDISR6_VALUE 0x00000001
/*
* pwr mgmt features supported in the soc-specific code:
* value == 0x0, the soc code does not support this feature
* value != 0x0, the soc code supports this feature
*/
#define SOC_CORE_RELEASE 0x1
#define SOC_CORE_RESTART 0x1
#define SOC_CORE_OFF 0x1
#define SOC_CORE_STANDBY 0x1
#define SOC_CORE_PWR_DWN 0x1
#define SOC_CLUSTER_STANDBY 0x1
#define SOC_CLUSTER_PWR_DWN 0x1
#define SOC_SYSTEM_STANDBY 0x1
#define SOC_SYSTEM_PWR_DWN 0x1
#define SOC_SYSTEM_OFF 0x1
#define SOC_SYSTEM_RESET 0x1
#define SYSTEM_PWR_DOMAINS 1
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
NUMBER_OF_CLUSTERS + \
SYSTEM_PWR_DOMAINS)
/* Power state coordination occurs at the system level */
#define PLAT_PD_COORD_LVL MPIDR_AFFLVL2
#define PLAT_MAX_PWR_LVL PLAT_PD_COORD_LVL
/* Local power state for power domains in Run state */
#define LS_LOCAL_STATE_RUN PSCI_LOCAL_STATE_RUN
/* define retention state */
#define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1)
#define LS_LOCAL_STATE_RET PLAT_MAX_RET_STATE
/* define power-down state */
#define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
#define LS_LOCAL_STATE_OFF PLAT_MAX_OFF_STATE
#ifndef __ASSEMBLER__
/* CCI slave interfaces */
static const int cci_map[] = {
3,
4,
};
void soc_init_lowlevel(void);
void soc_init_percpu(void);
void _soc_set_start_addr(unsigned long addr);
void _set_platform_security(void);
#endif
#endif /* SOC_H */

397
plat/nxp/soc-ls1088a/soc.c Normal file
View file

@ -0,0 +1,397 @@
/*
* Copyright 2022 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <arch.h>
#include <caam.h>
#include <cci.h>
#include <common/debug.h>
#include <dcfg.h>
#ifdef I2C_INIT
#include <i2c.h>
#endif
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <ls_interconnect.h>
#if TRUSTED_BOARD_BOOT
#include <nxp_smmu.h>
#endif
#include <nxp_timer.h>
#include <plat_console.h>
#include <plat_gic.h>
#include <plat_tzc400.h>
#include <pmu.h>
#if defined(NXP_SFP_ENABLED)
#include <sfp.h>
#endif
#include <errata.h>
#ifdef CONFIG_OCRAM_ECC_EN
#include <ocram.h>
#endif
#include <plat_common.h>
#include <platform_def.h>
#include <soc.h>
static unsigned char _power_domain_tree_desc[NUMBER_OF_CLUSTERS + 2];
static struct soc_type soc_list[] = {
SOC_ENTRY(LS1044A, LS1044A, 1, 4),
SOC_ENTRY(LS1044AE, LS1044AE, 1, 4),
SOC_ENTRY(LS1048A, LS1048A, 1, 4),
SOC_ENTRY(LS1048AE, LS1048AE, 1, 4),
SOC_ENTRY(LS1084A, LS1084A, 2, 4),
SOC_ENTRY(LS1084AE, LS1084AE, 2, 4),
SOC_ENTRY(LS1088A, LS1088A, 2, 4),
SOC_ENTRY(LS1088AE, LS1088AE, 2, 4),
};
static dcfg_init_info_t dcfg_init_data = {
.g_nxp_dcfg_addr = NXP_DCFG_ADDR,
.nxp_sysclk_freq = NXP_SYSCLK_FREQ,
.nxp_ddrclk_freq = NXP_DDRCLK_FREQ,
.nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER,
};
/*
* This function dynamically constructs the topology according to
* SoC Flavor and returns it.
*/
const unsigned char *plat_get_power_domain_tree_desc(void)
{
unsigned int i;
uint8_t num_clusters, cores_per_cluster;
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
/*
* The highest level is the system level. The next level is constituted
* by clusters and then cores in clusters.
*/
_power_domain_tree_desc[0] = 1;
_power_domain_tree_desc[1] = num_clusters;
for (i = 0; i < _power_domain_tree_desc[1]; i++) {
_power_domain_tree_desc[i + 2] = cores_per_cluster;
}
return _power_domain_tree_desc;
}
CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256,
assert_invalid_ls1088a_cluster_count);
/*
* This function returns the core count within the cluster corresponding to
* `mpidr`.
*/
unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr)
{
return CORES_PER_CLUSTER;
}
/*
* This function returns the total number of cores in the SoC
*/
unsigned int get_tot_num_cores(void)
{
uint8_t num_clusters, cores_per_cluster;
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
return (num_clusters * cores_per_cluster);
}
/*
* This function returns the PMU IDLE Cluster mask.
*/
unsigned int get_pmu_idle_cluster_mask(void)
{
uint8_t num_clusters, cores_per_cluster;
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
return ((1 << num_clusters) - 2);
}
/*
* This function returns the PMU Flush Cluster mask.
*/
unsigned int get_pmu_flush_cluster_mask(void)
{
uint8_t num_clusters, cores_per_cluster;
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
return ((1 << num_clusters) - 2);
}
/*
* This function returns the PMU IDLE Core mask.
*/
unsigned int get_pmu_idle_core_mask(void)
{
return ((1 << get_tot_num_cores()) - 2);
}
#ifdef IMAGE_BL2
void soc_bl2_prepare_exit(void)
{
#if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE)
set_sfp_wr_disable();
#endif
}
void soc_preload_setup(void)
{
}
/*
* This function returns the boot device based on RCW_SRC
*/
enum boot_device get_boot_dev(void)
{
enum boot_device src = BOOT_DEVICE_NONE;
uint32_t porsr1;
uint32_t rcw_src, val;
porsr1 = read_reg_porsr1();
rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT;
/* RCW SRC NOR */
val = rcw_src & RCW_SRC_TYPE_MASK;
if (val == NOR_16B_VAL) {
src = BOOT_DEVICE_IFC_NOR;
INFO("RCW BOOT SRC is IFC NOR\n");
} else {
val = rcw_src & RCW_SRC_SERIAL_MASK;
switch (val) {
case QSPI_VAL:
src = BOOT_DEVICE_QSPI;
INFO("RCW BOOT SRC is QSPI\n");
break;
case SDHC_VAL:
src = BOOT_DEVICE_EMMC;
INFO("RCW BOOT SRC is SD/EMMC\n");
break;
case EMMC_VAL:
src = BOOT_DEVICE_EMMC;
INFO("RCW BOOT SRC is SD/EMMC\n");
break;
default:
src = BOOT_DEVICE_NONE;
}
}
return src;
}
/*
* This function sets up access permissions on memory regions
*/
void soc_mem_access(void)
{
dram_regions_info_t *info_dram_regions = get_dram_regions_info();
int i = 0;
struct tzc400_reg tzc400_reg_list[MAX_NUM_TZC_REGION];
int dram_idx, index = 1;
for (dram_idx = 0; dram_idx < info_dram_regions->num_dram_regions;
dram_idx++) {
if (info_dram_regions->region[i].size == 0) {
ERROR("DDR init failure, or");
ERROR("DRAM regions not populated correctly.\n");
break;
}
index = populate_tzc400_reg_list(tzc400_reg_list,
dram_idx, index,
info_dram_regions->region[dram_idx].addr,
info_dram_regions->region[dram_idx].size,
NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE);
}
mem_access_setup(NXP_TZC_ADDR, index,
tzc400_reg_list);
}
/*
* This function implements soc specific erratum
* This is called before DDR is initialized or MMU is enabled
*/
void soc_early_init(void)
{
enum boot_device dev;
dram_regions_info_t *dram_regions_info = get_dram_regions_info();
#ifdef CONFIG_OCRAM_ECC_EN
ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE);
#endif
dcfg_init(&dcfg_init_data);
#if LOG_LEVEL > 0
/* Initialize the console to provide early debug support */
plat_console_init(NXP_CONSOLE_ADDR,
NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
#endif
enable_timer_base_to_cluster(NXP_PMU_ADDR);
enable_core_tb(NXP_PMU_ADDR);
/*
* Use the region(NXP_SD_BLOCK_BUF_ADDR + NXP_SD_BLOCK_BUF_SIZE)
* as dma of sd
*/
dev = get_boot_dev();
if (dev == BOOT_DEVICE_EMMC) {
mmap_add_region(NXP_SD_BLOCK_BUF_ADDR, NXP_SD_BLOCK_BUF_ADDR,
NXP_SD_BLOCK_BUF_SIZE,
MT_DEVICE | MT_RW | MT_NS);
}
#if TRUSTED_BOARD_BOOT
uint32_t mode;
sfp_init(NXP_SFP_ADDR);
/*
* For secure boot disable SMMU.
* Later when platform security policy comes in picture,
* this might get modified based on the policy
*/
if (check_boot_mode_secure(&mode) == true) {
bypass_smmu(NXP_SMMU_ADDR);
}
/*
* For Mbedtls currently crypto is not supported via CAAM
* enable it when that support is there. In tbbr.mk
* the CAAM_INTEG is set as 0.
*/
#ifndef MBEDTLS_X509
/* Initialize the crypto accelerator if enabled */
if (is_sec_enabled() == false) {
INFO("SEC is disabled.\n");
} else {
sec_init(NXP_CAAM_ADDR);
}
#endif
#endif
soc_errata();
delay_timer_init(NXP_TIMER_ADDR);
i2c_init(NXP_I2C_ADDR);
dram_regions_info->total_dram_size = init_ddr();
}
#else /* !IMAGE_BL2 */
void soc_early_platform_setup2(void)
{
dcfg_init(&dcfg_init_data);
/*
* Initialize system level generic timer for Socs
*/
delay_timer_init(NXP_TIMER_ADDR);
#if LOG_LEVEL > 0
/* Initialize the console to provide early debug support */
plat_console_init(NXP_CONSOLE_ADDR,
NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
#endif
}
void soc_platform_setup(void)
{
/* Initialize the GIC driver, cpu and distributor interfaces */
static uintptr_t target_mask_array[PLATFORM_CORE_COUNT];
static interrupt_prop_t ls_interrupt_props[] = {
PLAT_LS_G1S_IRQ_PROPS(INTR_GROUP1S),
PLAT_LS_G0_IRQ_PROPS(INTR_GROUP0)
};
plat_ls_gic_driver_init(NXP_GICD_ADDR, NXP_GICR_ADDR,
PLATFORM_CORE_COUNT,
ls_interrupt_props,
ARRAY_SIZE(ls_interrupt_props),
target_mask_array,
plat_core_pos);
plat_ls_gic_init();
enable_init_timer();
}
/*
* This function initializes the soc from the BL31 module
*/
void soc_init(void)
{
uint8_t num_clusters, cores_per_cluster;
/* low-level init of the soc */
soc_init_lowlevel();
_init_global_data();
soc_init_percpu();
_initialize_psci();
/*
* Initialize Interconnect for this cluster during cold boot.
* No need for locks as no other CPU is active.
*/
cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map));
/*
* Enable Interconnect coherency for the primary CPU's cluster.
*/
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
plat_ls_interconnect_enter_coherency(num_clusters);
/* set platform security policies */
_set_platform_security();
/* Initialize the crypto accelerator if enabled */
if (is_sec_enabled() == false) {
INFO("SEC is disabled.\n");
} else {
sec_init(NXP_CAAM_ADDR);
}
}
void soc_runtime_setup(void)
{
}
#endif /* IMAGE_BL2 */
/*
* Function to return the SoC SYS CLK
*/
unsigned int get_sys_clk(void)
{
return NXP_SYSCLK_FREQ;
}
/*
* Function returns the base counter frequency
* after reading the first entry at CNTFID0 (0x20 offset).
*
* Function is used by:
* 1. ARM common code for PSCI management.
* 2. ARM Generic Timer init.
*/
unsigned int plat_get_syscnt_freq2(void)
{
unsigned int counter_base_frequency;
/*
* Below register specifies the base frequency of the system counter.
* As per NXP Board Manuals:
* The system counter always works with SYS_REF_CLK/4 frequency clock.
*/
counter_base_frequency = mmio_read_32(NXP_TIMER_ADDR + CNTFID_OFF);
return counter_base_frequency;
}

87
plat/nxp/soc-ls1088a/soc.def Normal file
View file

@ -0,0 +1,87 @@
#
# Copyright 2022 NXP
#
# SPDX-License-Identifier: BSD-3-Clause
#
#
#------------------------------------------------------------------------------
#
# This file contains the basic architecture definitions that drive the build
#
# -----------------------------------------------------------------------------
CORE_TYPE := a53
CACHE_LINE := 6
# Set to GIC400 or GIC500
GIC := GIC500
# Set to CCI400 or CCN504 or CCN508
INTERCONNECT := CCI400
# Select the DDR PHY generation to be used
PLAT_DDR_PHY := PHY_GEN1
PHYS_SYS := 64
# Indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
CHASSIS := 3
# TZC IP Details TZC used is TZC380 or TZC400
TZC_ID := TZC400
# CONSOLE Details available is NS16550 or PL011
CONSOLE := NS16550
NXP_SFP_VER := 3_4
# In IMAGE_BL2, compile time flag for handling Cache coherency
# with CAAM for BL2 running from OCRAM
SEC_MEM_NON_COHERENT := yes
# OCRAM MAP for BL2
# Before BL2
# 0x18000000 - 0x18009fff -> Used by ROM code, (TBD - can it be used for xlat tables)
# 0x1800a000 - 0x1801Cfff -> Reserved for BL2 binary (76 KB)
# 0x1801D000 - 0x1801ffff -> CSF header for BL2 (12 KB)
OCRAM_START_ADDR := 0x18000000
OCRAM_SIZE := 0x20000
CSF_HDR_SZ := 0x3000
# Area of OCRAM reserved by ROM code
NXP_ROM_RSVD := 0xa000
# Input to CST create_hdr_isbc tool
BL2_HDR_LOC := 0x1801D000
# Location of BL2 on OCRAM
# BL2_BASE=OCRAM_START_ADDR+NXP_ROM_RSVD
BL2_BASE := 0x1800a000
# SoC ERRATUM to be enabled
ERRATA_SOC_A008850 := 1
# ARM Erratum
ERRATA_A53_855873 := 1
# DDR Erratum
ERRATA_DDR_A008511 := 1
ERRATA_DDR_A009803 := 1
ERRATA_DDR_A009942 := 1
ERRATA_DDR_A010165 := 1
# Define Endianness of each module
NXP_ESDHC_ENDIANNESS := LE
NXP_SFP_ENDIANNESS := LE
NXP_GPIO_ENDIANNESS := LE
NXP_SNVS_ENDIANNESS := LE
NXP_GUR_ENDIANNESS := LE
NXP_SEC_ENDIANNESS := LE
NXP_DDR_ENDIANNESS := LE
NXP_QSPI_ENDIANNESS := LE
# OCRAM ECC Enabled
OCRAM_ECC_EN := yes

110
plat/nxp/soc-ls1088a/soc.mk Normal file
View file

@ -0,0 +1,110 @@
#
# Copyright 2022 NXP
#
# SPDX-License-Identifier: BSD-3-Clause
#
# SoC-specific build parameters
SOC := ls1088a
PLAT_PATH := plat/nxp
PLAT_COMMON_PATH:= plat/nxp/common
PLAT_DRIVERS_PATH:= drivers/nxp
PLAT_SOC_PATH := ${PLAT_PATH}/soc-${SOC}
BOARD_PATH := ${PLAT_SOC_PATH}/${BOARD}
# Separate BL2 NOLOAD region (.bss, stack, page tables). need to
# define BL2_NOLOAD_START and BL2_NOLOAD_LIMIT
SEPARATE_BL2_NOLOAD_REGION := 1
# get SoC-specific defnitions
include ${PLAT_SOC_PATH}/soc.def
include ${PLAT_COMMON_PATH}/plat_make_helper/soc_common_def.mk
include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
# For Security Features
DISABLE_FUSE_WRITE := 1
ifeq (${TRUSTED_BOARD_BOOT}, 1)
ifeq (${GENERATE_COT},1)
# Save Keys to be used by DDR FIP image
SAVE_KEYS=1
endif
$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
# Used by create_pbl tool to
# create bl2_<boot_mode>_sec.pbl image
SECURE_BOOT := yes
endif
$(eval $(call SET_NXP_MAKE_FLAG,CRYPTO_NEEDED,BL_COMM))
# Selecting Drivers for SoC
$(eval $(call SET_NXP_MAKE_FLAG,DCFG_NEEDED,BL_COMM))
$(eval $(call SET_NXP_MAKE_FLAG,TIMER_NEEDED,BL_COMM))
$(eval $(call SET_NXP_MAKE_FLAG,INTERCONNECT_NEEDED,BL_COMM))
$(eval $(call SET_NXP_MAKE_FLAG,GIC_NEEDED,BL31))
$(eval $(call SET_NXP_MAKE_FLAG,CONSOLE_NEEDED,BL_COMM))
$(eval $(call SET_NXP_MAKE_FLAG,PMU_NEEDED,BL_COMM))
$(eval $(call SET_NXP_MAKE_FLAG,DDR_DRIVER_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,TZASC_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,I2C_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,IMG_LOADR_NEEDED,BL2))
# Selecting PSCI & SIP_SVC support
$(eval $(call SET_NXP_MAKE_FLAG,PSCI_NEEDED,BL31))
$(eval $(call SET_NXP_MAKE_FLAG,SIPSVC_NEEDED,BL31))
# Adding SoC specific files
include ${PLAT_COMMON_PATH}/soc_errata/errata.mk
PLAT_INCLUDES += -I${PLAT_COMMON_PATH}/include/default\
-I${BOARD_PATH}\
-I${PLAT_COMMON_PATH}/include/default/ch_${CHASSIS}\
-I${PLAT_COMMON_PATH}/soc_errata\
-I${PLAT_COMMON_PATH}/include\
-I${PLAT_SOC_PATH}/include
ifeq (${SECURE_BOOT},yes)
include ${PLAT_COMMON_PATH}/tbbr/tbbr.mk
endif
ifeq (${PSCI_NEEDED}, yes)
include ${PLAT_COMMON_PATH}/psci/psci.mk
endif
ifeq (${SIPSVC_NEEDED}, yes)
include ${PLAT_COMMON_PATH}/sip_svc/sipsvc.mk
endif
# for fuse-fip & fuse-programming
ifeq (${FUSE_PROG}, 1)
include ${PLAT_COMMON_PATH}/fip_handler/fuse_fip/fuse.mk
endif
ifeq (${IMG_LOADR_NEEDED},yes)
include $(PLAT_COMMON_PATH)/img_loadr/img_loadr.mk
endif
# Adding source files for the above selected drivers.
include ${PLAT_DRIVERS_PATH}/drivers.mk
PLAT_BL_COMMON_SOURCES += ${PLAT_COMMON_PATH}/$(ARCH)/ls_helpers.S\
${PLAT_SOC_PATH}/${ARCH}/${SOC}_helpers.S\
${PLAT_SOC_PATH}/soc.c
BL31_SOURCES += ${PLAT_SOC_PATH}/$(ARCH)/${SOC}.S\
${PSCI_SOURCES}\
${SIPSVC_SOURCES}\
${PLAT_COMMON_PATH}/$(ARCH)/bl31_data.S
ifeq (${TEST_BL31}, 1)
BL31_SOURCES += ${PLAT_SOC_PATH}/$(ARCH)/bootmain64.S \
${PLAT_SOC_PATH}/$(ARCH)/nonboot64.S
endif
BL2_SOURCES += ${DDR_CNTLR_SOURCES}\
${TBBR_SOURCES}\
${FUSE_SOURCES}
# Adding TFA setup files
include ${PLAT_PATH}/common/setup/common.mk