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https://github.com/ARM-software/arm-trusted-firmware.git
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Merge changes from topic "morello-dt-fix" into integration
* changes: fix(morello): dts: remove #a-c and #s-c from memory node fix(morello): dts: fix GICv3 compatible string fix(morello): dts: fix DT node naming fix(morello): dts: fix SCMI shmem/mboxes grouping fix(morello): dts: use documented DPU compatible string fix(morello): dts: fix DP SMMU IRQ ordering fix(morello): dts: fix SMMU IRQ ordering fix(morello): dts: add model names fix(morello): dts: fix stdout-path target
This commit is contained in:
Manish V Badarkhe
TrustedFirmware Code Review
commit
9dedc1ab21
3 changed files with 28 additions and 34 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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* Copyright (c) 2020-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -8,6 +8,7 @@
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#include "morello.dtsi"
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/ {
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model = "Arm Morello Fixed Virtual Platform";
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chosen {
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stdout-path = "serial0:115200n8";
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@ -78,16 +79,12 @@
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/* The first bank of memory, memory map is actually provided by UEFI. */
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memory@80000000 {
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#address-cells = <2>;
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#size-cells = <2>;
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device_type = "memory";
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/* [0x80000000-0xffffffff] */
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reg = <0x00000000 0x80000000 0x0 0x80000000>;
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};
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memory@8080000000 {
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#address-cells = <2>;
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#size-cells = <2>;
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device_type = "memory";
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/* [0x8080000000-0x83ffffffff] */
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reg = <0x00000080 0x80000000 0x1 0x80000000>;
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@ -143,8 +140,8 @@
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scmi {
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compatible = "arm,scmi";
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mbox-names = "tx", "rx";
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mboxes = <&mailbox 1 0 &mailbox 1 1>;
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shmem = <&cpu_scp_hpri0 &cpu_scp_hpri1>;
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mboxes = <&mailbox 1 0>, <&mailbox 1 1>;
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shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -8,9 +8,10 @@
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#include "morello.dtsi"
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/ {
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model = "Arm Morello System Development Platform";
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chosen {
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stdout-path = "soc_uart0:115200n8";
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stdout-path = "serial0:115200n8";
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};
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reserved-memory {
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@ -59,16 +60,12 @@
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/* The first bank of memory, memory map is actually provided by UEFI. */
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memory@80000000 {
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#address-cells = <2>;
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#size-cells = <2>;
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device_type = "memory";
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/* [0x80000000-0xffffffff] */
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reg = <0x00000000 0x80000000 0x0 0x7F000000>;
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};
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memory@8080000000 {
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#address-cells = <2>;
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#size-cells = <2>;
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device_type = "memory";
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/* [0x8080000000-0x83f7ffffff] */
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reg = <0x00000080 0x80000000 0x3 0x78000000>;
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@ -78,10 +75,10 @@
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compatible = "arm,smmu-v3";
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reg = <0 0x4f400000 0 0x40000>;
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interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 237 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 237 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
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<GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
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msi-parent = <&its2 0>;
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#iommu-cells = <1>;
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dma-coherent;
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@ -114,10 +111,10 @@
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compatible = "arm,smmu-v3";
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reg = <0 0x4f000000 0 0x40000>;
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interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 230 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
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<GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
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msi-parent = <&its1 0>;
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#iommu-cells = <1>;
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dma-coherent;
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@ -150,16 +147,16 @@
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compatible = "arm,smmu-v3";
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reg = <0 0x2ce00000 0 0x40000>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 80 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "cmdq-sync", "gerror";
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<GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "gerror", "cmdq-sync";
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#iommu-cells = <1>;
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};
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dp0: display@2cc00000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "arm,mali-d32";
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compatible = "arm,mali-d32", "arm,mali-d71";
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reg = <0 0x2cc00000 0 0x20000>;
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interrupts = <0 69 4>;
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interrupt-names = "DPU";
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@ -220,8 +217,8 @@
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scmi {
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compatible = "arm,scmi";
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mbox-names = "tx", "rx";
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mboxes = <&mailbox 1 0 &mailbox 1 1>;
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shmem = <&cpu_scp_hpri0 &cpu_scp_hpri1>;
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mboxes = <&mailbox 1 0>, <&mailbox 1 1>;
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shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>;
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_dvfs: protocol@13 {
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@ -241,28 +238,28 @@
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<0x0 0x300c0000 0 0x80000>; /* GICR */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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its1: its@30040000 {
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its1: msi-controller@30040000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x0 0x30040000 0x0 0x20000>;
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};
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its2: its@30060000 {
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its2: msi-controller@30060000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x0 0x30060000 0x0 0x20000>;
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};
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its_ccix: its@30080000 {
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its_ccix: msi-controller@30080000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x0 0x30080000 0x0 0x20000>;
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};
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its_pcie: its@300a0000 {
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its_pcie: msi-controller@300a0000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2020-2021, Arm Limited. All rights reserved.
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* Copyright (c) 2020-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -18,7 +18,7 @@
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};
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gic: interrupt-controller@2c010000 {
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compatible = "arm,gic-600", "arm,gic-v3";
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compatible = "arm,gic-v3";
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#address-cells = <2>;
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#interrupt-cells = <3>;
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#size-cells = <2>;
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@ -70,12 +70,12 @@
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#size-cells = <1>;
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ranges = <0 0x0 0x06000000 0x8000>;
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cpu_scp_hpri0: scp-shmem@0 {
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cpu_scp_hpri0: scp-sram@0 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x80>;
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};
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cpu_scp_hpri1: scp-shmem@80 {
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cpu_scp_hpri1: scp-sram@80 {
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compatible = "arm,scmi-shmem";
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reg = <0x80 0x80>;
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};
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@ -95,7 +95,7 @@
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clock-output-names = "uartclk";
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};
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soc_uart0: uart@2a400000 {
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soc_uart0: serial@2a400000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x2a400000 0x0 0x1000>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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