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feat(nxp-clk): add CGM0 instance

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Introduce the MC_CGM0 instance responsible for XBAR and other peripheral
clocks.

Change-Id: Icf1e9ce6e71e4ff446835d1e7b6522bfb6f2b4b6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
This commit is contained in:
Ghennadi Procopciuc 2024-08-05 16:50:52 +03:00
parent 4cd04c50eb
commit 9dbca85ddf
3 changed files with 10 additions and 0 deletions
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1
drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h
View file

@ -10,6 +10,7 @@
#define FXOSC_BASE_ADDR (0x40050000UL) #define FXOSC_BASE_ADDR (0x40050000UL)
#define ARMPLL_BASE_ADDR (0x40038000UL) #define ARMPLL_BASE_ADDR (0x40038000UL)
#define ARM_DFS_BASE_ADDR (0x40054000UL) #define ARM_DFS_BASE_ADDR (0x40054000UL)
#define CGM0_BASE_ADDR (0x40030000UL)
#define CGM1_BASE_ADDR (0x40034000UL) #define CGM1_BASE_ADDR (0x40034000UL)
/* FXOSC */ /* FXOSC */

8
drivers/nxp/clk/s32cc/s32cc_clk_drv.c
View file

@ -23,6 +23,7 @@ struct s32cc_clk_drv {
uintptr_t fxosc_base; uintptr_t fxosc_base;
uintptr_t armpll_base; uintptr_t armpll_base;
uintptr_t armdfs_base; uintptr_t armdfs_base;
uintptr_t cgm0_base;
uintptr_t cgm1_base; uintptr_t cgm1_base;
}; };
@ -42,6 +43,7 @@ static struct s32cc_clk_drv *get_drv(void)
.fxosc_base = FXOSC_BASE_ADDR, .fxosc_base = FXOSC_BASE_ADDR,
.armpll_base = ARMPLL_BASE_ADDR, .armpll_base = ARMPLL_BASE_ADDR,
.armdfs_base = ARM_DFS_BASE_ADDR, .armdfs_base = ARM_DFS_BASE_ADDR,
.cgm0_base = CGM0_BASE_ADDR,
.cgm1_base = CGM1_BASE_ADDR, .cgm1_base = CGM1_BASE_ADDR,
}; };
@ -92,6 +94,9 @@ static int get_base_addr(enum s32cc_clk_source id, const struct s32cc_clk_drv *d
case S32CC_ARM_DFS: case S32CC_ARM_DFS:
*base = drv->armdfs_base; *base = drv->armdfs_base;
break; break;
case S32CC_CGM0:
*base = drv->cgm0_base;
break;
case S32CC_CGM1: case S32CC_CGM1:
*base = drv->cgm1_base; *base = drv->cgm1_base;
break; break;
@ -547,6 +552,9 @@ static int enable_mux(const struct s32cc_clk_obj *module,
case S32CC_CGM1: case S32CC_CGM1:
ret = enable_cgm_mux(mux, drv); ret = enable_cgm_mux(mux, drv);
break; break;
case S32CC_CGM0:
ret = enable_cgm_mux(mux, drv);
break;
default: default:
ERROR("Unknown mux parent type: %d\n", mux->module); ERROR("Unknown mux parent type: %d\n", mux->module);
ret = -EINVAL; ret = -EINVAL;

1
include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
View file

@ -30,6 +30,7 @@ enum s32cc_clk_source {
S32CC_SIRC, S32CC_SIRC,
S32CC_ARM_PLL, S32CC_ARM_PLL,
S32CC_ARM_DFS, S32CC_ARM_DFS,
S32CC_CGM0,
S32CC_CGM1, S32CC_CGM1,
}; };