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refactor(drivers/marvell/comphy-3700): rename Miscellaneous Control register constants

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Rename the Miscellaneous Control register constants from MISC_REGx to
MISC_CTRLx.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I4d43bbda44b090de4ecf2d52cfc468f9683cc3b5
This commit is contained in:
Marek Behún 2021-12-08 01:20:50 +01:00
parent 86f6b55d47
commit 9cf978c6c4
2 changed files with 11 additions and 11 deletions
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12
drivers/marvell/comphy/phy-comphy-3700.c
View file

@ -450,7 +450,7 @@ static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index,
*/
data = 0;
mask = PHY_REF_CLK_SEL;
reg_set16(SGMIIPHY_ADDR(COMPHY_MISC_REG0, sd_ip_addr), data, mask);
reg_set16(SGMIIPHY_ADDR(COMPHY_MISC_CTRL0, sd_ip_addr), data, mask);
/*
* 9. Set correct reference clock frequency in COMPHY register
@ -731,8 +731,8 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
/*
* 10. Enable the output of 500M clock
*/
data = MISC_REG0_DEFAULT_VALUE | CLK500M_EN;
usb3_reg_set(reg_base, COMPHY_MISC_REG0, data, REG_16_BIT_MASK);
data = MISC_CTRL0_DEFAULT_VALUE | CLK500M_EN;
usb3_reg_set(reg_base, COMPHY_MISC_CTRL0, data, REG_16_BIT_MASK);
/*
* 11. Set 20-bit data width
@ -829,7 +829,7 @@ static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index,
CFG_SEL_20B, CFG_SEL_20B);
/* 3. Force to use reg setting for PCIe mode */
reg_set16(MISC_REG1_ADDR(PCIE) + COMPHY_SD_ADDR,
reg_set16(MISC_CTRL1_ADDR(PCIE) + COMPHY_SD_ADDR,
SEL_BITS_PCIE_FORCE, SEL_BITS_PCIE_FORCE);
/* 4. Change RX wait */
@ -843,8 +843,8 @@ static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index,
IDLE_SYNC_EN_DEFAULT_VALUE | IDLE_SYNC_EN, REG_16_BIT_MASK);
/* 6. Enable the output of 100M/125M/500M clock */
reg_set16(MISC_REG0_ADDR(PCIE) + COMPHY_SD_ADDR,
MISC_REG0_DEFAULT_VALUE | CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN,
reg_set16(MISC_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR,
MISC_CTRL0_DEFAULT_VALUE | CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN,
REG_16_BIT_MASK);
/*

10
drivers/marvell/comphy/phy-comphy-3700.h
View file

@ -122,16 +122,16 @@ enum {
#define IDLE_SYNC_EN BIT(12)
#define IDLE_SYNC_EN_DEFAULT_VALUE 0x60
#define COMPHY_MISC_REG0 0x4F
#define MISC_REG0_ADDR(unit) (COMPHY_MISC_REG0 * PHY_SHFT(unit))
#define COMPHY_MISC_CTRL0 0x4F
#define MISC_CTRL0_ADDR(unit) (COMPHY_MISC_CTRL0 * PHY_SHFT(unit))
#define CLK100M_125M_EN BIT(4)
#define TXDCLK_2X_SEL BIT(6)
#define CLK500M_EN BIT(7)
#define PHY_REF_CLK_SEL BIT(10)
#define MISC_REG0_DEFAULT_VALUE 0xA00D
#define MISC_CTRL0_DEFAULT_VALUE 0xA00D
#define COMPHY_MISC_REG1 0x73
#define MISC_REG1_ADDR(unit) (COMPHY_MISC_REG1 * PHY_SHFT(unit))
#define COMPHY_MISC_CTRL1 0x73
#define MISC_CTRL1_ADDR(unit) (COMPHY_MISC_CTRL1 * PHY_SHFT(unit))
#define SEL_BITS_PCIE_FORCE BIT(15)
#define COMPHY_GEN2_SET3 0x112