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plat: marvell: a3700: do not power off cpu due to errata ref #13

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Do not power off the CPU1 since there is no way to wake it up
(wake-up is causing CPU0 reset as well duo to HW bug). Quote from errata
Ref #13 [In power saving mode, both cores must be powered off]:
"When Core 0 is on and Core 1 is in power-off state, a Core 1
wake-up resets Core 0 as well and puts Core 0 back to ROM".

To overcome described HW bug instead of powering the CPU off, let it
reach WFI instruction, which is invoked by generic psci_do_cpu_off
function after platform handler finishes. This will put the core in low
power state and give a chance to wake it up.

Before this change, after running secondary kernel via kexec, only one
core was up, now both cores are up.

Change-Id: I87f144867550728055d9b8a2edb84a14539acab7
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
This commit is contained in:
Grzegorz Jaszczyk 2018-11-14 18:47:35 +01:00 • committed by Konstantin Porotchkin
parent 0529106c4b
commit 9cb6751d59
1 changed files with 0 additions and 9 deletions
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9
plat/marvell/a3700/common/plat_pm.c
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@ -288,18 +288,9 @@ int a3700_validate_ns_entrypoint(uintptr_t entrypoint)
*/
void a3700_pwr_domain_off(const psci_power_state_t *target_state)
{
uint32_t cpu_idx = plat_my_core_pos();
/* Prevent interrupts from spuriously waking up this cpu */
plat_marvell_gic_cpuif_disable();
/*
* Enable Core VDD OFF, core is supposed to be powered
* off by PMU when WFI command is issued.
*/
mmio_setbits_32(MVEBU_PM_CPU_0_PWR_CTRL_REG + 4 * cpu_idx,
MVEBU_PM_CORE_PD);
/* Core can not be powered down with pending IRQ,
* acknowledge all the pending IRQ
*/