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Merge "fix(versal2): correct the UFS clock rates" into integration

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Joanna Farley 2024-10-16 15:24:41 +02:00 • committed by TrustedFirmware Code Review
commit 9c05fcf662
1 changed files with 7 additions and 2 deletions
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9
plat/amd/versal2/scmi.c
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@ -51,8 +51,8 @@ static struct scmi_clk scmi0_clock[] = {
CLOCK_CELL(CLK_SERIAL1_0, CLK_SERIAL1_0, "uart1_uartclk", true, 100000000), CLOCK_CELL(CLK_SERIAL1_0, CLK_SERIAL1_0, "uart1_uartclk", true, 100000000),
CLOCK_CELL(CLK_SERIAL1_1, CLK_SERIAL1_1, "uart1_apb_pclk", true, 100000000), CLOCK_CELL(CLK_SERIAL1_1, CLK_SERIAL1_1, "uart1_apb_pclk", true, 100000000),
CLOCK_CELL(CLK_UFS0_0, CLK_UFS0_0, "ufs_core_clk", true, 100000000), CLOCK_CELL(CLK_UFS0_0, CLK_UFS0_0, "ufs_core_clk", true, 100000000),
CLOCK_CELL(CLK_UFS0_1, CLK_UFS0_1, "ufs_phy_clk", true, 100000000), CLOCK_CELL(CLK_UFS0_1, CLK_UFS0_1, "ufs_phy_clk", true, 26000000),
CLOCK_CELL(CLK_UFS0_2, CLK_UFS0_2, "ufs_ref_pclk", true, 100000000), CLOCK_CELL(CLK_UFS0_2, CLK_UFS0_2, "ufs_ref_pclk", true, 26000000),
CLOCK_CELL(CLK_USB0_0, CLK_USB0_0, "usb0_bus_clk", true, 100000000), CLOCK_CELL(CLK_USB0_0, CLK_USB0_0, "usb0_bus_clk", true, 100000000),
CLOCK_CELL(CLK_USB0_1, CLK_USB0_1, "usb0_ref_clk", true, 100000000), CLOCK_CELL(CLK_USB0_1, CLK_USB0_1, "usb0_ref_clk", true, 100000000),
CLOCK_CELL(CLK_USB0_2, CLK_USB0_2, "usb0_dwc_clk", true, 100000000), CLOCK_CELL(CLK_USB0_2, CLK_USB0_2, "usb0_dwc_clk", true, 100000000),
@ -649,6 +649,11 @@ void init_scmi_server(void)
/* Keep i2c on 100MHz to calculate rates properly */ /* Keep i2c on 100MHz to calculate rates properly */
if (i >= CLK_I2C0_0 && i <= CLK_I2C7_0) if (i >= CLK_I2C0_0 && i <= CLK_I2C7_0)
continue; continue;
/* Keep UFS clocks to default values to get the expected rates */
if (i >= CLK_UFS0_0 && i <= CLK_UFS0_2)
continue;
/* /*
* SPP supports multiple versions. * SPP supports multiple versions.
* The cpu_clock value is set to corresponding SPP * The cpu_clock value is set to corresponding SPP