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Merge pull request #1681 from Andre-ARM/allwinner/fixes

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allwinner: clock / power fixes
This commit is contained in:
Antonio Niño Díaz 2018-11-23 10:18:23 +01:00 • committed by GitHub
commit 98aab97484
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GPG key ID: 4AEE18F83AFDEB23
2 changed files with 33 additions and 6 deletions
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20
plat/allwinner/common/sunxi_bl31_setup.c
View file

@ -11,6 +11,7 @@
#include <generic_delay_timer.h> #include <generic_delay_timer.h>
#include <gicv2.h> #include <gicv2.h>
#include <libfdt.h> #include <libfdt.h>
#include <mmio.h>
#include <platform.h> #include <platform.h>
#include <platform_def.h> #include <platform_def.h>
#include <sunxi_def.h> #include <sunxi_def.h>
@ -148,6 +149,25 @@ void bl31_platform_setup(void)
sunxi_security_setup(); sunxi_security_setup();
/*
* On the A64 U-Boot's SPL sets the bus clocks to some conservative
* values, to work around FEL mode instabilities with SRAM C accesses.
* FEL mode is gone when we reach ATF, so bring the AHB1 bus
* (the "main" bus) clock frequency back to the recommended 200MHz,
* for improved performance.
*/
if (soc_id == SUNXI_SOC_A64)
mmio_write_32(SUNXI_CCU_BASE + 0x54, 0x00003180);
/*
* U-Boot or the kernel don't setup AHB2, which leaves it at the
* AHB1 frequency (200 MHz, see above). However Allwinner recommends
* 300 MHz, for improved Ethernet and USB performance. Switch the
* clock to use "PLL_PERIPH0 / 2".
*/
if (soc_id == SUNXI_SOC_A64 || soc_id == SUNXI_SOC_H5)
mmio_write_32(SUNXI_CCU_BASE + 0x5c, 0x1);
sunxi_pmic_setup(soc_id, fdt); sunxi_pmic_setup(soc_id, fdt);
INFO("BL31: Platform setup done\n"); INFO("BL31: Platform setup done\n");

19
plat/allwinner/sun50i_a64/sunxi_power.c
View file

@ -118,7 +118,7 @@ static int axp_write(uint8_t reg, uint8_t val)
return rsb_write(AXP803_RT_ADDR, reg, val); return rsb_write(AXP803_RT_ADDR, reg, val);
} }
static int axp_setbits(uint8_t reg, uint8_t set_mask) static int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask)
{ {
uint8_t regval; uint8_t regval;
int ret; int ret;
@ -127,11 +127,14 @@ static int axp_setbits(uint8_t reg, uint8_t set_mask)
if (ret < 0) if (ret < 0)
return ret; return ret;
regval = ret | set_mask; regval = (ret & ~clr_mask) | set_mask;
return rsb_write(AXP803_RT_ADDR, reg, regval); return rsb_write(AXP803_RT_ADDR, reg, regval);
} }
#define axp_clrbits(reg, clr_mask) axp_clrsetbits(reg, clr_mask, 0)
#define axp_setbits(reg, set_mask) axp_clrsetbits(reg, 0, set_mask)
static bool should_enable_regulator(const void *fdt, int node) static bool should_enable_regulator(const void *fdt, int node)
{ {
if (fdt_getprop(fdt, node, "phandle", NULL) != NULL) if (fdt_getprop(fdt, node, "phandle", NULL) != NULL)
@ -178,8 +181,9 @@ struct axp_regulator {
unsigned char switch_reg; unsigned char switch_reg;
unsigned char switch_bit; unsigned char switch_bit;
} regulators[] = { } regulators[] = {
{"dcdc1", 1600, 3400, 100, NO_SPLIT, 0x20, 0xff, 9}, {"dcdc1", 1600, 3400, 100, NO_SPLIT, 0x20, 0x10, 0},
{"dcdc5", 800, 1840, 10, 32, 0x24, 0xff, 9}, {"dcdc5", 800, 1840, 10, 32, 0x24, 0x10, 4},
{"dcdc6", 600, 1520, 10, 50, 0x25, 0x10, 5},
{"dldo1", 700, 3300, 100, NO_SPLIT, 0x15, 0x12, 3}, {"dldo1", 700, 3300, 100, NO_SPLIT, 0x15, 0x12, 3},
{"dldo2", 700, 4200, 100, 27, 0x16, 0x12, 4}, {"dldo2", 700, 4200, 100, 27, 0x16, 0x12, 4},
{"dldo3", 700, 3300, 100, NO_SPLIT, 0x17, 0x12, 5}, {"dldo3", 700, 3300, 100, NO_SPLIT, 0x17, 0x12, 5},
@ -226,8 +230,11 @@ static void setup_axp803_rails(const void *fdt)
return; return;
} }
if (fdt_getprop(fdt, node, "x-powers,drive-vbus-en", NULL)) if (fdt_getprop(fdt, node, "x-powers,drive-vbus-en", NULL)) {
axp_setbits(0x8f, BIT(4)); axp_clrbits(0x8f, BIT(4));
axp_setbits(0x30, BIT(2));
INFO("PMIC: AXP803: Enabling DRIVEVBUS\n");
}
/* descend into the "regulators" subnode */ /* descend into the "regulators" subnode */
node = fdt_first_subnode(fdt, node); node = fdt_first_subnode(fdt, node);