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Merge changes from topic "srm/errata" into integration
* changes: fix(cpus): workaround for Neoverse V1 errata 2779461 fix(cpus): workaround for Cortex-A78 erratum 2779479
This commit is contained in:
Bipin Ravi
TrustedFirmware Code Review
commit
982f8e1997
6 changed files with 103 additions and 4 deletions
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@ -321,6 +321,10 @@ For Cortex-A78, the following errata build flags are defined :
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CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
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it is still open.
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- ``ERRATA_A78_2779479``: This applies erratum 2779479 workaround to Cortex-A78
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CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and
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it is still open.
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For Cortex-A78 AE, the following errata build flags are defined :
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- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to
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@ -468,6 +472,10 @@ For Neoverse V1, the following errata build flags are defined :
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CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the
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CPU. It is still open.
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- ``ERRATA_V1_2779461``: This applies erratum 2779461 workaround to Neoverse-V1
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CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the
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CPU. It is still open.
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For Cortex-A710, the following errata build flags are defined :
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- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019-2022, ARM Limited. All rights reserved.
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* Copyright (c) 2019-2023, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -40,6 +40,8 @@
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#define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
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#define CORTEX_A78_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
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#define CORTEX_A78_ACTLR3_EL1 S3_0_C15_C1_2
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/*******************************************************************************
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* CPU Activity Monitor Unit register specific definitions.
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******************************************************************************/
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019-2022, ARM Limited. All rights reserved.
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* Copyright (c) 2019-2023, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -41,4 +41,6 @@
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#define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28)
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#define NEOVERSE_V1_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
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#define NEOVERSE_V1_ACTLR3_EL1 S3_0_C15_C1_2
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#endif /* NEOVERSE_V1_H */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019-2022, ARM Limited. All rights reserved.
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* Copyright (c) 2019-2023, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -351,6 +351,35 @@ func check_errata_2772019
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b cpu_rev_var_ls
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endfunc check_errata_2772019
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/* ----------------------------------------------------
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* Errata Workaround for Cortex A78 Errata 2779479.
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* This applies to revisions r0p0, r1p0, r1p1, and r1p2.
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* It is still open.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x1, x17
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* ----------------------------------------------------
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*/
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func errata_a78_2779479_wa
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/* Check revision. */
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mov x17, x30
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bl check_errata_2779479
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cbz x0, 1f
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/* Apply the workaround */
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mrs x1, CORTEX_A78_ACTLR3_EL1
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orr x1, x1, #BIT(47)
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msr CORTEX_A78_ACTLR3_EL1, x1
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1:
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ret x17
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endfunc errata_a78_2779479_wa
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func check_errata_2779479
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/* Applies to r0p0, r1p0, r1p1, r1p2 */
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mov x1, #CPU_REV(1, 2)
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b cpu_rev_var_ls
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endfunc check_errata_2779479
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func check_errata_cve_2022_23960
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#if WORKAROUND_CVE_2022_23960
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mov x0, #ERRATA_APPLIES
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@ -414,6 +443,11 @@ func cortex_a78_reset_func
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bl errata_a78_2395406_wa
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#endif
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#if ERRATA_A78_2779479
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mov x0, x18
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bl errata_a78_2779479_wa
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#endif
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#if ENABLE_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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@ -493,6 +527,7 @@ func cortex_a78_errata_report
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report_errata ERRATA_A78_2376745, cortex_a78, 2376745
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report_errata ERRATA_A78_2395406, cortex_a78, 2395406
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report_errata ERRATA_A78_2772019, cortex_a78, 2772019
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report_errata ERRATA_A78_2779479, cortex_a78, 2779479
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report_errata WORKAROUND_CVE_2022_23960, cortex_a78, cve_2022_23960
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ldp x8, x30, [sp], #16
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019-2022, Arm Limited. All rights reserved.
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* Copyright (c) 2019-2023, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -486,6 +486,35 @@ func check_errata_2743093
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b cpu_rev_var_ls
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endfunc check_errata_2743093
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/* ----------------------------------------------------
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* Errata Workaround for Neoverse V1 Errata #2779461.
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* This applies to revisions r0p0, r1p0, r1p1, and r1p2.
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* It is still open.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x1, x17
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* ----------------------------------------------------
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*/
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func errata_neoverse_v1_2779461_wa
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/* Check revision. */
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mov x17, x30
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bl check_errata_2779461
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cbz x0, 1f
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/* Apply the workaround */
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mrs x1, NEOVERSE_V1_ACTLR3_EL1
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orr x1, x1, #BIT(47)
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msr NEOVERSE_V1_ACTLR3_EL1, x1
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1:
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ret x17
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endfunc errata_neoverse_v1_2779461_wa
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func check_errata_2779461
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/* Applies to r0p0, r1p0, r1p1, r1p2 */
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mov x1, #CPU_REV(1, 2)
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b cpu_rev_var_ls
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endfunc check_errata_2779461
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func check_errata_cve_2022_23960
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#if WORKAROUND_CVE_2022_23960
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mov x0, #ERRATA_APPLIES
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@ -544,6 +573,7 @@ func neoverse_v1_errata_report
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report_errata ERRATA_V1_2294912, neoverse_v1, 2294912
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report_errata ERRATA_V1_2372203, neoverse_v1, 2372203
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report_errata ERRATA_V1_2743093, neoverse_v1, 2743093
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report_errata ERRATA_V1_2779461, neoverse_v1, 2779461
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report_errata WORKAROUND_CVE_2022_23960, neoverse_v1, cve_2022_23960
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ldp x8, x30, [sp], #16
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@ -622,6 +652,11 @@ func neoverse_v1_reset_func
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bl errata_neoverse_v1_2372203_wa
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#endif
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#if ERRATA_V1_2779461
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mov x0, x18
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bl errata_neoverse_v1_2779461_wa
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#endif
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#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
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/*
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* The Neoverse-V1 generic vectors are overridden to apply errata
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@ -362,6 +362,10 @@ ERRATA_A78_2395406 ?=0
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# open.
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ERRATA_A78_2772019 ?=0
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# Flag to apply erratum 2779479 workaround during reset. This erratum applies
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# to revision r0p0, r1p0, r1p1 and r1p2 of the A78 cpu. It is still open.
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ERRATA_A78_2779479 ?=0
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# Flag to apply erratum 1941500 workaround during reset. This erratum applies
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# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
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ERRATA_A78_AE_1941500 ?=0
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@ -522,6 +526,11 @@ ERRATA_V1_2372203 ?=0
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# still open.
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ERRATA_V1_2743093 ?=0
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# Flag to apply erratum 2779461 workaround during powerdown. This erratum
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# applies to revisions r0p0, r1p0, r1p1 and r1p2 of the Neoverse V1 cpu and is
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# still open.
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ERRATA_V1_2779461 ?=0
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# Flag to apply erratum 1987031 workaround during reset. This erratum applies
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# to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
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ERRATA_A710_1987031 ?=0
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@ -1030,6 +1039,10 @@ $(eval $(call add_define,ERRATA_A78_2395406))
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$(eval $(call assert_boolean,ERRATA_A78_2772019))
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$(eval $(call add_define,ERRATA_A78_2772019))
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# Process ERRATA_A78_2779479 flag
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$(eval $(call assert_boolean,ERRATA_A78_2779479))
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$(eval $(call add_define,ERRATA_A78_2779479))
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# Process ERRATA_A78_AE_1941500 flag
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$(eval $(call assert_boolean,ERRATA_A78_AE_1941500))
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$(eval $(call add_define,ERRATA_A78_AE_1941500))
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@ -1186,6 +1199,10 @@ $(eval $(call add_define,ERRATA_V1_2372203))
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$(eval $(call assert_boolean,ERRATA_V1_2743093))
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$(eval $(call add_define,ERRATA_V1_2743093))
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# Process ERRATA_V1_2779461 flag
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$(eval $(call assert_boolean,ERRATA_V1_2779461))
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$(eval $(call add_define,ERRATA_V1_2779461))
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# Process ERRATA_A710_1987031 flag
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$(eval $(call assert_boolean,ERRATA_A710_1987031))
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$(eval $(call add_define,ERRATA_A710_1987031))
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