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Merge "Fix exception handlers in BL31: Use DSB to synchronize pending EA" into integration
This commit is contained in:
Madhukar Pappireddy
TrustedFirmware Code Review
commit
96edbe0341
4 changed files with 103 additions and 7 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -15,6 +15,7 @@
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#include <context.h>
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.globl handle_lower_el_ea_esb
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.globl handle_lower_el_async_ea
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.globl enter_lower_el_sync_ea
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.globl enter_lower_el_async_ea
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@ -133,6 +134,7 @@ func enter_lower_el_async_ea
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*/
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str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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handle_lower_el_async_ea:
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/*
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* Save general purpose and ARMv8.3-PAuth registers (if enabled).
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* If Secure Cycle Counter is not disabled in MDCR_EL3 when
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -45,8 +45,9 @@
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* instruction. When an error is thus synchronized, the handling is
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* delegated to platform EA handler.
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*
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* Without RAS_EXTENSION, this macro just saves x30, and unmasks
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* Asynchronous External Aborts.
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* Without RAS_EXTENSION, this macro synchronizes pending errors using
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* a DSB, unmasks Asynchronous External Aborts and saves X30 before
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* setting the flag CTX_IS_IN_EL3.
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*/
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.macro check_and_unmask_ea
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#if RAS_EXTENSION
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@ -79,13 +80,89 @@
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bl restore_gp_pmcr_pauth_regs
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1:
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#else
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/*
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* For SoCs which do not implement RAS, use DSB as a barrier to
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* synchronize pending external aborts.
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*/
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dsb sy
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/* Unmask the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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/* Use ISB for the above unmask operation to take effect immediately */
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isb
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/*
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* Refer Note 1. No need to restore X30 as both handle_sync_exception
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* and handle_interrupt_exception macro which follow this macro modify
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* X30 anyway.
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*/
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str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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mov x30, #1
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str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
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dmb sy
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#endif
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.endm
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#if !RAS_EXTENSION
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/*
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* Note 1: The explicit DSB at the entry of various exception vectors
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* for handling exceptions from lower ELs can inadvertently trigger an
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* SError exception in EL3 due to pending asynchronous aborts in lower
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* ELs. This will end up being handled by serror_sp_elx which will
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* ultimately panic and die.
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* The way to workaround is to update a flag to indicate if the exception
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* truly came from EL3. This flag is allocated in the cpu_context
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* structure and located at offset "CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3"
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* This is not a bullet proof solution to the problem at hand because
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* we assume the instructions following "isb" that help to update the
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* flag execute without causing further exceptions.
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*/
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/* ---------------------------------------------------------------------
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* This macro handles Asynchronous External Aborts.
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* ---------------------------------------------------------------------
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*/
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.macro handle_async_ea
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/*
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* Use a barrier to synchronize pending external aborts.
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*/
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dsb sy
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/* Unmask the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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/* Use ISB for the above unmask operation to take effect immediately */
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isb
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/* Refer Note 1 */
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str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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mov x30, #1
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str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
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dmb sy
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b handle_lower_el_async_ea
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.endm
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/*
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* This macro checks if the exception was taken due to SError in EL3 or
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* because of pending asynchronous external aborts from lower EL that got
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* triggered due to explicit synchronization in EL3. Refer Note 1.
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*/
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.macro check_if_serror_from_EL3
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/* Assumes SP_EL3 on entry */
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str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
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cbnz x30, exp_from_EL3
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/* Handle asynchronous external abort from lower EL */
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b handle_lower_el_async_ea
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exp_from_EL3:
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/* Jump to plat_handle_el3_ea which does not return */
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.endm
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#endif
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/* ---------------------------------------------------------------------
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* This macro handles Synchronous exceptions.
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* Only SMC exceptions are supported.
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@ -272,6 +349,9 @@ vector_entry fiq_sp_elx
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end_vector_entry fiq_sp_elx
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vector_entry serror_sp_elx
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#if !RAS_EXTENSION
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check_if_serror_from_EL3
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#endif
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no_ret plat_handle_el3_ea
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end_vector_entry serror_sp_elx
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@ -305,8 +385,12 @@ end_vector_entry fiq_aarch64
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vector_entry serror_aarch64
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apply_at_speculative_wa
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#if RAS_EXTENSION
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msr daifclr, #DAIF_ABT_BIT
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b enter_lower_el_async_ea
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#else
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handle_async_ea
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#endif
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end_vector_entry serror_aarch64
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/* ---------------------------------------------------------------------
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@ -339,8 +423,12 @@ end_vector_entry fiq_aarch32
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vector_entry serror_aarch32
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apply_at_speculative_wa
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#if RAS_EXTENSION
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msr daifclr, #DAIF_ABT_BIT
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b enter_lower_el_async_ea
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#else
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handle_async_ea
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#endif
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end_vector_entry serror_aarch32
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#ifdef MONITOR_TRAPS
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -60,7 +60,8 @@
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#define CTX_SPSR_EL3 U(0x18)
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#define CTX_ELR_EL3 U(0x20)
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#define CTX_PMCR_EL0 U(0x28)
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#define CTX_EL3STATE_END U(0x30)
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#define CTX_IS_IN_EL3 U(0x30)
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#define CTX_EL3STATE_END U(0x40) /* Align to the next 16 byte boundary */
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/*******************************************************************************
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* Constants that allow assembler code to access members of and the
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -995,6 +995,11 @@ func el3_exit
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* ----------------------------------------------------------
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*/
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esb
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#else
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dsb sy
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#endif
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#ifdef IMAGE_BL31
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str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
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#endif
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exception_return
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