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feat(smccc): add bit definition for SMCCC_ARCH_SOC_ID

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The definitions of SMCCC_ARCH_SOC_ID SoC version return bits are defined
in SMC Calling Convention [1]. Add the masks and shifts for JEP-106 bank
index, JEP-106 identification code, and Implementation defined SoC ID.
Add a macro to easily set JEP-106 fields.

 [1] https://developer.arm.com/documentation/den0028/latest/

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Iecbd09f6de6728de89dc746d2d1981a5a97a8ab7
This commit is contained in:
Yann Gautier 2021-05-20 10:32:22 +02:00
parent e55d12b7eb
commit 96b0596ea2
1 changed files with 18 additions and 1 deletions
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19
include/lib/smccc.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -50,6 +50,23 @@
#define GET_SMC_OEN(id) (((id) >> FUNCID_OEN_SHIFT) & \
FUNCID_OEN_MASK)
/*******************************************************************************
* SMCCC_ARCH_SOC_ID SoC version & revision bit definition
******************************************************************************/
#define SOC_ID_JEP_106_BANK_IDX_MASK GENMASK_32(30, 24)
#define SOC_ID_JEP_106_BANK_IDX_SHIFT U(24)
#define SOC_ID_JEP_106_ID_CODE_MASK GENMASK_32(23, 16)
#define SOC_ID_JEP_106_ID_CODE_SHIFT U(16)
#define SOC_ID_IMPL_DEF_MASK GENMASK_32(15, 0)
#define SOC_ID_IMPL_DEF_SHIFT U(0)
#define SOC_ID_SET_JEP_106(bkid, mfid) ((((bkid) << SOC_ID_JEP_106_BANK_IDX_SHIFT) & \
SOC_ID_JEP_106_BANK_IDX_MASK) | \
(((mfid) << SOC_ID_JEP_106_ID_CODE_SHIFT) & \
SOC_ID_JEP_106_ID_CODE_MASK))
#define SOC_ID_REV_MASK GENMASK_32(30, 0)
#define SOC_ID_REV_SHIFT U(0)
/*******************************************************************************
* Owning entity number definitions inside the function id as per the SMC
* calling convention