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errata: workaround for Cortex-A710 erratum 2083908

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Cortex-A710 erratum 2083908 is a Cat B erratum that applies to
revision r2p0 and is still open. The workaround is to set
CPUACTLR5_EL1[13] to 1.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I876d26a7ac6ab0d7c567a9ec9f34fc0f952589d8
This commit is contained in:
nayanpatel-arm 2021-09-16 15:27:53 -07:00
parent 95ef4a0f6b
commit 95fe195d53
4 changed files with 56 additions and 4 deletions
docs/design
cpu-specific-build-macros.rst
include/lib/cpus/aarch64
cortex_a710.h
lib/cpus
aarch64
cortex_a710.S
cpu-ops.mk

4
docs/design/cpu-specific-build-macros.rst
View file

@ -389,6 +389,10 @@ For Cortex-A710, the following errata build flags are defined :
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
of the CPU and is still open.
- ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to
Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and
is still open.
For Neoverse N2, the following errata build flags are defined :
- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2

10
include/lib/cpus/aarch64/cortex_a710.h
View file

@ -13,7 +13,7 @@
* CPU Extended Control register specific definitions
******************************************************************************/
#define CORTEX_A710_CPUECTLR_EL1 S3_0_C15_C1_4
#define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
#define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
/*******************************************************************************
* CPU Power Control register specific definitions
@ -25,6 +25,12 @@
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
#define CORTEX_A710_CPUACTLR_EL1 S3_0_C15_C1_0
#define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
#define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
#define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0
#define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
#endif /* CORTEX_A710_H */

38
lib/cpus/aarch64/cortex_a710.S
View file

@ -160,6 +160,34 @@ func check_errata_2017096
b cpu_rev_var_ls
endfunc check_errata_2017096
/* ---------------------------------------------------------------------
* Errata Workaround for Cortex-A710 Erratum 2083908.
* This applies to revision r2p0 of Cortex-A710 and is still open.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* ---------------------------------------------------------------------
*/
func errata_a710_2083908_wa
/* Compare x0 against revision r2p0 */
mov x17, x30
bl check_errata_2083908
cbz x0, 1f
mrs x1, CORTEX_A710_CPUACTLR5_EL1
orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_13
msr CORTEX_A710_CPUACTLR5_EL1, x1
1:
ret x17
endfunc errata_a710_2083908_wa
func check_errata_2083908
/* Applies to r2p0 */
mov x1, #CPU_REV(2, 0)
mov x2, #CPU_REV(2, 0)
b cpu_rev_var_range
endfunc check_errata_2083908
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
@ -194,6 +222,7 @@ func cortex_a710_errata_report
report_errata ERRATA_A710_2081180, cortex_a710, 2081180
report_errata ERRATA_A710_2055002, cortex_a710, 2055002
report_errata ERRATA_A710_2017096, cortex_a710, 2017096
report_errata ERRATA_A710_2083908, cortex_a710, 2083908
ldp x8, x30, [sp], #16
ret
@ -225,8 +254,13 @@ func cortex_a710_reset_func
#endif
#if ERRATA_A710_2017096
mov x0, x18
bl errata_a710_2017096_wa
mov x0, x18
bl errata_a710_2017096_wa
#endif
#if ERRATA_A710_2083908
mov x0, x18
bl errata_a710_2083908_wa
#endif
isb
ret x19

8
lib/cpus/cpu-ops.mk
View file

@ -425,6 +425,10 @@ ERRATA_A710_1987031 ?=0
# to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
ERRATA_A710_2081180 ?=0
# Flag to apply erratum 2083908 workaround during reset. This erratum applies
# to revision r2p0 of the Cortex-A710 cpu and is still open.
ERRATA_A710_2083908 ?=0
# Flag to apply erratum 2067956 workaround during reset. This erratum applies
# to revision r0p0 of the Neoverse N2 cpu and is still open.
ERRATA_N2_2067956 ?=0
@ -806,6 +810,10 @@ $(eval $(call add_define,ERRATA_A710_1987031))
$(eval $(call assert_boolean,ERRATA_A710_2081180))
$(eval $(call add_define,ERRATA_A710_2081180))
# Process ERRATA_A710_2083908 flag
$(eval $(call assert_boolean,ERRATA_A710_2083908))
$(eval $(call add_define,ERRATA_A710_2083908))
# Process ERRATA_N2_2067956 flag
$(eval $(call assert_boolean,ERRATA_N2_2067956))
$(eval $(call add_define,ERRATA_N2_2067956))