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feat(cpus): add support for Alto CPU

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Add basic CPU library code to support the Alto CPU.

Change-Id: I45958be99c4a350a32a9e511d3705fb568b97236
Signed-off-by: Igor Podgainõi <igor.podgainoi@arm.com>
This commit is contained in:
Igor Podgainõi 2024-11-29 15:01:54 +01:00
parent 15e5c6c91d
commit 940ecd072c
3 changed files with 97 additions and 1 deletions
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29
include/lib/cpus/aarch64/cortex_alto.h Normal file
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@ -0,0 +1,29 @@
/*
* Copyright (c) 2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef CORTEX_ALTO_H
#define CORTEX_ALTO_H
#define CORTEX_ALTO_MIDR U(0x411FD900)
/*******************************************************************************
* CPU Extended Control register specific definitions
******************************************************************************/
#define CORTEX_ALTO_IMP_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
#define CORTEX_ALTO_IMP_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_ALTO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
/*******************************************************************************
* SME Control registers
******************************************************************************/
#define CORTEX_ALTO_SVCRSM S0_3_C4_C2_3
#define CORTEX_ALTO_SVCRZA S0_3_C4_C4_3
#endif /* CORTEX_ALTO_H */

66
lib/cpus/aarch64/cortex_alto.S Normal file
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@ -0,0 +1,66 @@
/*
* Copyright (c) 2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <common/bl_common.h>
#include <cortex_alto.h>
#include <cpu_macros.S>
#include <plat_macros.S>
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Alto must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
#error "Alto supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
cpu_reset_func_start cortex_alto
/* Disable speculative loads */
msr SSBS, xzr
cpu_reset_func_end cortex_alto
func cortex_alto_core_pwr_dwn
#if ENABLE_SME_FOR_NS
/* ---------------------------------------------------
* Disable SME if enabled and supported
* ---------------------------------------------------
*/
mrs x0, ID_AA64PFR1_EL1
ubfx x0, x0, #ID_AA64PFR1_EL1_SME_SHIFT, \
#ID_AA64PFR1_EL1_SME_WIDTH
cmp x0, #SME_NOT_IMPLEMENTED
b.eq 1f
msr CORTEX_ALTO_SVCRSM, xzr
msr CORTEX_ALTO_SVCRZA, xzr
1:
#endif
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
sysreg_bit_set CORTEX_ALTO_IMP_CPUPWRCTLR_EL1, \
CORTEX_ALTO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
isb
ret
endfunc cortex_alto_core_pwr_dwn
.section .rodata.cortex_alto_regs, "aS"
cortex_alto_regs: /* The ASCII list of register names to be reported */
.asciz "cpuectlr_el1", ""
func cortex_alto_cpu_reg_dump
adr x6, cortex_alto_regs
mrs x8, CORTEX_ALTO_IMP_CPUECTLR_EL1
ret
endfunc cortex_alto_cpu_reg_dump
declare_cpu_ops cortex_alto, CORTEX_ALTO_MIDR, \
cortex_alto_reset_func, \
cortex_alto_core_pwr_dwn

3
plat/arm/board/fvp/platform.mk
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@ -218,7 +218,8 @@ ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1)
lib/cpus/aarch64/cortex_gelas.S \
lib/cpus/aarch64/nevis.S \
lib/cpus/aarch64/travis.S \
lib/cpus/aarch64/cortex_arcadia.S
lib/cpus/aarch64/cortex_arcadia.S \
lib/cpus/aarch64/cortex_alto.S
endif
else