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Merge "feat(imx8mq): add 100us delay after USB OTG SRC bit 0 clear" into integration

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This commit is contained in:
Madhukar Pappireddy 2022-06-06 16:18:20 +02:00 • committed by TrustedFirmware Code Review
commit 938dfa2968
1 changed files with 10 additions and 2 deletions
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12
plat/imx/imx8m/imx8mq/gpc.c
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@ -9,6 +9,7 @@
#include <stdbool.h>
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <lib/mmio.h>
#include <lib/psci/psci.h>
#include <platform_def.h>
@ -176,6 +177,13 @@ void imx_gpc_init(void)
mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1);
mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1);
/* enable all the power domain by default */
mmio_write_32(IMX_GPC_BASE + PU_PGC_UP_TRG, 0x3fcf);
/*
* for USB OTG, the limitation are:
* 1. before system clock config, the IPG clock run at 12.5MHz, delay time
* should be longer than 82us.
* 2. after system clock config, ipg clock run at 66.5MHz, delay time
* be longer that 15.3 us.
* Add 100us to make sure the USB OTG SRC is clear safely.
*/
udelay(100);
}