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fix(cm): update gic el2 sysregs save/restore mechanism

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This patch does following two changes
- Create a separate routine for saving/restoring GIC el2 system registers
- To access ICC_SRE_EL2 register there was a workaround to set
  SCR_EL3.NS before accessing it. This was required because SCR_EL3.EEL2
  was zero. But with commit f105dd5fa this bit has been set to one early
  on in booting process for a system with FEAT_SEL2 present and S-EL2
  enabled.
  However, we still need the workaround for a system which needs
  save/restore of EL2 registers without secure EL2 being enabled e.g.
  system with Non-secure and Realm world present.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I8d55c3dc6a17c4749748822d4a738912c1e13298
This commit is contained in:
Manish Pandey 2024-02-05 21:40:21 +00:00
parent 514d022fda
commit 937d6fdb70
1 changed files with 50 additions and 35 deletions
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85
lib/el3_runtime/aarch64/context_mgmt.c
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@ -1134,13 +1134,58 @@ static void el2_sysregs_context_restore_mpam(mpam_t *ctx)
}
#endif /* CTX_INCLUDE_MPAM_REGS */
/* ---------------------------------------------------------------------------
* The following registers are not added:
* ICH_AP0R<n>_EL2
* ICH_AP1R<n>_EL2
* ICH_LR<n>_EL2
*
* NOTE: For a system with S-EL2 present but not enabled, accessing
* ICC_SRE_EL2 is undefined from EL3. To workaround this change the
* SCR_EL3.NS = 1 before accessing this register.
* ---------------------------------------------------------------------------
*/
static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx)
{
#if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
write_ctx_reg(ctx, CTX_ICC_SRE_EL2, read_icc_sre_el2());
#else
u_register_t scr_el3 = read_scr_el3();
write_scr_el3(scr_el3 | SCR_NS_BIT);
isb();
write_ctx_reg(ctx, CTX_ICC_SRE_EL2, read_icc_sre_el2());
write_scr_el3(scr_el3);
isb();
#endif
write_ctx_reg(ctx, CTX_ICH_HCR_EL2, read_ich_hcr_el2());
write_ctx_reg(ctx, CTX_ICH_VMCR_EL2, read_ich_vmcr_el2());
}
static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx)
{
#if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
write_icc_sre_el2(read_ctx_reg(ctx, CTX_ICC_SRE_EL2));
#else
u_register_t scr_el3 = read_scr_el3();
write_scr_el3(scr_el3 | SCR_NS_BIT);
isb();
write_icc_sre_el2(read_ctx_reg(ctx, CTX_ICC_SRE_EL2));
write_scr_el3(scr_el3);
isb();
#endif
write_ich_hcr_el2(read_ctx_reg(ctx, CTX_ICH_HCR_EL2));
write_ich_vmcr_el2(read_ctx_reg(ctx, CTX_ICH_VMCR_EL2));
}
/* -----------------------------------------------------
* The following registers are not added:
* AMEVCNTVOFF0<n>_EL2
* AMEVCNTVOFF1<n>_EL2
* ICH_AP0R<n>_EL2
* ICH_AP1R<n>_EL2
* ICH_LR<n>_EL2
* -----------------------------------------------------
*/
static void el2_sysregs_context_save_common(el2_sysregs_t *ctx)
@ -1162,22 +1207,6 @@ static void el2_sysregs_context_save_common(el2_sysregs_t *ctx)
write_ctx_reg(ctx, CTX_HCR_EL2, read_hcr_el2());
write_ctx_reg(ctx, CTX_HPFAR_EL2, read_hpfar_el2());
write_ctx_reg(ctx, CTX_HSTR_EL2, read_hstr_el2());
/*
* Set the NS bit to be able to access the ICC_SRE_EL2 register
* TODO: remove with root context
*/
u_register_t scr_el3 = read_scr_el3();
write_scr_el3(scr_el3 | SCR_NS_BIT);
isb();
write_ctx_reg(ctx, CTX_ICC_SRE_EL2, read_icc_sre_el2());
write_scr_el3(scr_el3);
isb();
write_ctx_reg(ctx, CTX_ICH_HCR_EL2, read_ich_hcr_el2());
write_ctx_reg(ctx, CTX_ICH_VMCR_EL2, read_ich_vmcr_el2());
write_ctx_reg(ctx, CTX_MAIR_EL2, read_mair_el2());
write_ctx_reg(ctx, CTX_MDCR_EL2, read_mdcr_el2());
write_ctx_reg(ctx, CTX_SCTLR_EL2, read_sctlr_el2());
@ -1212,22 +1241,6 @@ static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx)
write_hcr_el2(read_ctx_reg(ctx, CTX_HCR_EL2));
write_hpfar_el2(read_ctx_reg(ctx, CTX_HPFAR_EL2));
write_hstr_el2(read_ctx_reg(ctx, CTX_HSTR_EL2));
/*
* Set the NS bit to be able to access the ICC_SRE_EL2 register
* TODO: remove with root context
*/
u_register_t scr_el3 = read_scr_el3();
write_scr_el3(scr_el3 | SCR_NS_BIT);
isb();
write_icc_sre_el2(read_ctx_reg(ctx, CTX_ICC_SRE_EL2));
write_scr_el3(scr_el3);
isb();
write_ich_hcr_el2(read_ctx_reg(ctx, CTX_ICH_HCR_EL2));
write_ich_vmcr_el2(read_ctx_reg(ctx, CTX_ICH_VMCR_EL2));
write_mair_el2(read_ctx_reg(ctx, CTX_MAIR_EL2));
write_mdcr_el2(read_ctx_reg(ctx, CTX_MDCR_EL2));
write_sctlr_el2(read_ctx_reg(ctx, CTX_SCTLR_EL2));
@ -1257,6 +1270,7 @@ void cm_el2_sysregs_context_save(uint32_t security_state)
el2_sysregs_ctx = get_el2_sysregs_ctx(ctx);
el2_sysregs_context_save_common(el2_sysregs_ctx);
el2_sysregs_context_save_gic(el2_sysregs_ctx);
if (is_feat_mte2_supported()) {
write_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2, read_tfsr_el2());
@ -1336,6 +1350,7 @@ void cm_el2_sysregs_context_restore(uint32_t security_state)
el2_sysregs_ctx = get_el2_sysregs_ctx(ctx);
el2_sysregs_context_restore_common(el2_sysregs_ctx);
el2_sysregs_context_restore_gic(el2_sysregs_ctx);
if (is_feat_mte2_supported()) {
write_tfsr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2));