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Merge changes I7d3a97df,I5935b4bc,I9a325c5b,Ie29bd3a5,Iebb90cf2 into integration

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* changes:
  fix(cpus): workaround for Cortex-A710 erratum 2291219
  fix(cpus): workaround for Cortex-X3 erratum 2313909
  fix(cpus): workaround for Neoverse-N2 erratum 2326639
  fix(rpi3): tighten platform pwr_domain_pwr_down_wfi behaviour
  chore: rename Makalu ELP to Cortex-X3
This commit is contained in:
Bipin Ravi 2022-10-27 19:21:46 +02:00 • committed by TrustedFirmware Code Review
commit 92b62c16b7
13 changed files with 217 additions and 61 deletions
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14
docs/design/cpu-specific-build-macros.rst
View file

@ -495,6 +495,10 @@ For Cortex-A710, the following errata build flags are defined :
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
of the CPU and is fixed in r2p1.
- ``ERRATA_A710_2291219``: This applies errata 2291219 workaround to
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
of the CPU and is fixed in r2p1.
- ``ERRATA_A710_2008768``: This applies errata 2008768 workaround to
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
of the CPU and is fixed in r2p1.
@ -535,6 +539,10 @@ For Neoverse N2, the following errata build flags are defined :
- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2
CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
- ``ERRATA_N2_2326639``: This applies errata 2326639 workaround to Neoverse-N2
CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
r0p1.
- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2
CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
r0p1.
@ -576,6 +584,12 @@ For Cortex-X2, the following errata build flags are defined :
Cortex-X2 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
of the CPU and is fixed in r2p1.
For Cortex-X3, the following errata build flags are defined :
- ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to
Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0
of the CPU, it is fixed in r1p1.
For Cortex-A510, the following errata build flags are defined :
- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to

3
docs/getting_started/porting-guide.rst
View file

@ -2769,7 +2769,8 @@ must ensure that races between multiple CPUs cannot occur.
The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()``
operation and it encodes the platform coordinated target local power states for
the CPU power domain and its parent power domain levels. This function must
not return back to the caller.
not return back to the caller (by calling wfi in an infinite loop to ensure
some CPUs power down mitigations work properly).
If this function is not implemented by the platform, PSCI generic
implementation invokes ``psci_power_down_wfi()`` for power down.

2
docs/plat/arm/tc/index.rst
View file

@ -18,7 +18,7 @@ Currently, the main difference between TC0 (TARGET_PLATFORM=0), TC1
is the CPUs supported as below:
- TC0 has support for Cortex A510, Cortex A710 and Cortex X2.
- TC1 has support for Cortex A510, Cortex Makalu and Cortex Makalu ELP.
- TC1 has support for Cortex A510, Cortex Makalu and Cortex X3.
- TC2 has support for Hayes and Hunter Arm CPUs.

4
docs/security_advisories/security-advisory-tfv-9.rst
View file

@ -71,12 +71,12 @@ revisions of Cortex-A73 and Cortex-A75 that implements FEAT_CSV2).
+----------------------+
| Cortex-X2 |
+----------------------+
| Cortex-X3 |
+----------------------+
| Cortex-A710 |
+----------------------+
| Cortex-Makalu |
+----------------------+
| Cortex-Makalu-ELP |
+----------------------+
| Cortex-Hunter |
+----------------------+
| Neoverse-N1 |

1
include/lib/cpus/aarch64/cortex_a710.h
View file

@ -36,6 +36,7 @@
******************************************************************************/
#define CORTEX_A710_CPUACTLR2_EL1 S3_0_C15_C1_1
#define CORTEX_A710_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
#define CORTEX_A710_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
/*******************************************************************************
* CPU Auxiliary Control register 5 specific definitions.

26
include/lib/cpus/aarch64/cortex_makalu_elp_arm.h
View file

@ -1,26 +0,0 @@
/*
* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef CORTEX_MAKALU_ELP_ARM_H
#define CORTEX_MAKALU_ELP_ARM_H
#define CORTEX_MAKALU_ELP_ARM_MIDR U(0x410FD4E0)
/* Cortex Makalu ELP loop count for CVE-2022-23960 mitigation */
#define CORTEX_MAKALU_ELP_ARM_BHB_LOOP_COUNT U(132)
/*******************************************************************************
* CPU Extended Control register specific definitions
******************************************************************************/
#define CORTEX_MAKALU_ELP_ARM_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
#define CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#endif /* CORTEX_MAKALU_ELP_ARM_H */

32
include/lib/cpus/aarch64/cortex_x3.h Normal file
View file

@ -0,0 +1,32 @@
/*
* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef CORTEX_X3_H
#define CORTEX_X3_H
#define CORTEX_X3_MIDR U(0x410FD4E0)
/* Cortex-X3 loop count for CVE-2022-23960 mitigation */
#define CORTEX_X3_BHB_LOOP_COUNT U(132)
/*******************************************************************************
* CPU Extended Control register specific definitions
******************************************************************************/
#define CORTEX_X3_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
#define CORTEX_X3_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
/*******************************************************************************
* CPU Auxiliary Control register 2 specific definitions.
******************************************************************************/
#define CORTEX_X3_CPUACTLR2_EL1 S3_0_C15_C1_1
#define CORTEX_X3_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
#endif /* CORTEX_X3_H */

1
include/lib/cpus/aarch64/neoverse_n2.h
View file

@ -39,6 +39,7 @@
#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1
#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
/*******************************************************************************

36
lib/cpus/aarch64/cortex_a710.S
View file

@ -383,6 +383,34 @@ func check_errata_2282622
b cpu_rev_var_ls
endfunc check_errata_2282622
/* ------------------------------------------------------------------------
* Errata Workaround for Cortex-A710 Erratum 2291219 on power down request.
* This applies to revision <= r2p0 and is fixed in r2p1.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x1, x17
* ------------------------------------------------------------------------
*/
func errata_a710_2291219_wa
/* Check revision. */
mov x17, x30
bl check_errata_2291219
cbz x0, 1f
/* Set bit 36 in ACTLR2_EL1 */
mrs x1, CORTEX_A710_CPUACTLR2_EL1
orr x1, x1, #CORTEX_A710_CPUACTLR2_EL1_BIT_36
msr CORTEX_A710_CPUACTLR2_EL1, x1
1:
ret x17
endfunc errata_a710_2291219_wa
func check_errata_2291219
/* Applies to <= r2p0. */
mov x1, #0x20
b cpu_rev_var_ls
endfunc check_errata_2291219
/* ---------------------------------------------------------------
* Errata Workaround for Cortex-A710 Erratum 2008768.
* This applies to revision r0p0, r1p0 and r2p0.
@ -476,6 +504,13 @@ func cortex_a710_core_pwr_dwn
mov x30, x4
#endif
#if ERRATA_A710_2291219
mov x15, x30
bl cpu_get_rev_var
bl errata_a710_2291219_wa
mov x30, x15
#endif /* ERRATA_A710_2291219 */
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
@ -513,6 +548,7 @@ func cortex_a710_errata_report
report_errata ERRATA_A710_2008768, cortex_a710, 2008768
report_errata ERRATA_A710_2147715, cortex_a710, 2147715
report_errata ERRATA_A710_2216384, cortex_a710, 2216384
report_errata ERRATA_A710_2291219, cortex_a710, 2291219
report_errata ERRATA_A710_2371105, cortex_a710, 2371105
report_errata WORKAROUND_CVE_2022_23960, cortex_a710, cve_2022_23960
report_errata ERRATA_DSU_2313941, cortex_a710, dsu_2313941

94
lib/cpus/aarch64/cortex_x3.S
View file

@ -7,40 +7,47 @@
#include <arch.h>
#include <asm_macros.S>
#include <common/bl_common.h>
#include <cortex_makalu_elp_arm.h>
#include <cortex_x3.h>
#include <cpu_macros.S>
#include <plat_macros.S>
#include "wa_cve_2022_23960_bhb_vector.S"
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Cortex Makalu ELP must be compiled with HW_ASSISTED_COHERENCY enabled"
#error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
#error "Cortex Makalu ELP supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table CORTEX_MAKALU_ELP_ARM_BHB_LOOP_COUNT, cortex_makalu_elp_arm
wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3
#endif /* WORKAROUND_CVE_2022_23960 */
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
*/
func cortex_makalu_elp_arm_core_pwr_dwn
func cortex_x3_core_pwr_dwn
#if ERRATA_X3_2313909
mov x15, x30
bl cpu_get_rev_var
bl errata_cortex_x3_2313909_wa
mov x30, x15
#endif /* ERRATA_X3_2313909 */
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
mrs x0, CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1, x0
mrs x0, CORTEX_X3_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr CORTEX_X3_CPUPWRCTLR_EL1, x0
isb
ret
endfunc cortex_makalu_elp_arm_core_pwr_dwn
endfunc cortex_x3_core_pwr_dwn
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
@ -51,28 +58,56 @@ func check_errata_cve_2022_23960
ret
endfunc check_errata_cve_2022_23960
func cortex_makalu_elp_arm_reset_func
func cortex_x3_reset_func
/* Disable speculative loads */
msr SSBS, xzr
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
/*
* The Cortex Makalu ELP generic vectors are overridden to apply
* The Cortex-X3 generic vectors are overridden to apply
* errata mitigation on exception entry from lower ELs.
*/
adr x0, wa_cve_vbar_cortex_makalu_elp_arm
adr x0, wa_cve_vbar_cortex_x3
msr vbar_el3, x0
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
isb
ret
endfunc cortex_makalu_elp_arm_reset_func
endfunc cortex_x3_reset_func
/* ----------------------------------------------------------------------
* Errata Workaround for Cortex-X3 Erratum 2313909 on power down request.
* This applies to revision r0p0 and r1p0 of Cortex-X3. Fixed in r1p1.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x1, x17
* ----------------------------------------------------------------------
*/
func errata_cortex_x3_2313909_wa
/* Check revision. */
mov x17, x30
bl check_errata_2313909
cbz x0, 1f
/* Set bit 36 in ACTLR2_EL1 */
mrs x1, CORTEX_X3_CPUACTLR2_EL1
orr x1, x1, #CORTEX_X3_CPUACTLR2_EL1_BIT_36
msr CORTEX_X3_CPUACTLR2_EL1, x1
1:
ret x17
endfunc errata_cortex_x3_2313909_wa
func check_errata_2313909
/* Applies to r0p0 and r1p0 */
mov x1, #0x10
b cpu_rev_var_ls
endfunc check_errata_2313909
#if REPORT_ERRATA
/*
* Errata printing function for Cortex Makalu ELP. Must follow AAPCS.
*/
func cortex_makalu_elp_arm_errata_report
/*
* Errata printing function for Cortex-X3. Must follow AAPCS.
*/
func cortex_x3_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
@ -82,15 +117,16 @@ func cortex_makalu_elp_arm_errata_report
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata WORKAROUND_CVE_2022_23960, cortex_makalu_elp_arm, cve_2022_23960
report_errata ERRATA_X3_2313909, cortex_x3, 2313909
report_errata WORKAROUND_CVE_2022_23960, cortex_x3, cve_2022_23960
ldp x8, x30, [sp], #16
ret
endfunc cortex_makalu_elp_arm_errata_report
endfunc cortex_x3_errata_report
#endif
/* ---------------------------------------------
* This function provides Cortex Makalu ELP-
* This function provides Cortex-X3-
* specific register information for crash
* reporting. It needs to return with x6
* pointing to a list of register names in ascii
@ -98,16 +134,16 @@ endfunc cortex_makalu_elp_arm_errata_report
* reported.
* ---------------------------------------------
*/
.section .rodata.cortex_makalu_elp_arm_regs, "aS"
cortex_makalu_elp_arm_regs: /* The ascii list of register names to be reported */
.section .rodata.cortex_x3_regs, "aS"
cortex_x3_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
func cortex_makalu_elp_arm_cpu_reg_dump
adr x6, cortex_makalu_elp_arm_regs
mrs x8, CORTEX_MAKALU_ELP_ARM_CPUECTLR_EL1
func cortex_x3_cpu_reg_dump
adr x6, cortex_x3_regs
mrs x8, CORTEX_X3_CPUECTLR_EL1
ret
endfunc cortex_makalu_elp_arm_cpu_reg_dump
endfunc cortex_x3_cpu_reg_dump
declare_cpu_ops cortex_makalu_elp_arm, CORTEX_MAKALU_ELP_ARM_MIDR, \
cortex_makalu_elp_arm_reset_func, \
cortex_makalu_elp_arm_core_pwr_dwn
declare_cpu_ops cortex_x3, CORTEX_X3_MIDR, \
cortex_x3_reset_func, \
cortex_x3_core_pwr_dwn

36
lib/cpus/aarch64/neoverse_n2.S
View file

@ -338,6 +338,34 @@ func check_errata_2280757
b cpu_rev_var_ls
endfunc check_errata_2280757
/* --------------------------------------------------
* Errata Workaround for Neoverse N2 Erratum 2326639.
* This applies to revision r0p0 of Neoverse N2,
* fixed in r0p1.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x1, x17
* --------------------------------------------------
*/
func errata_n2_2326639_wa
/* Check revision. */
mov x17, x30
bl check_errata_2326639
cbz x0, 1f
/* Set bit 36 in ACTLR2_EL1 */
mrs x1, NEOVERSE_N2_CPUACTLR2_EL1
orr x1, x1, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_36
msr NEOVERSE_N2_CPUACTLR2_EL1, x1
1:
ret x17
endfunc errata_n2_2326639_wa
func check_errata_2326639
/* Applies to r0p0, fixed in r0p1 */
mov x1, #0x00
b cpu_rev_var_ls
endfunc check_errata_2326639
/* --------------------------------------------------
* Errata Workaround for Neoverse N2 Erratum 2376738.
@ -533,6 +561,13 @@ func neoverse_n2_reset_func
endfunc neoverse_n2_reset_func
func neoverse_n2_core_pwr_dwn
#if ERRATA_N2_2326639
mov x15, x30
bl cpu_get_rev_var
bl errata_n2_2326639_wa
mov x30, x15
#endif /* ERRATA_N2_2326639 */
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* No need to do cache maintenance here.
@ -569,6 +604,7 @@ func neoverse_n2_errata_report
report_errata ERRATA_N2_2138958, neoverse_n2, 2138958
report_errata ERRATA_N2_2242400, neoverse_n2, 2242400
report_errata ERRATA_N2_2280757, neoverse_n2, 2280757
report_errata ERRATA_N2_2326639, neoverse_n2, 2326639
report_errata ERRATA_N2_2376738, neoverse_n2, 2376738
report_errata ERRATA_N2_2388450, neoverse_n2, 2388450
report_errata WORKAROUND_CVE_2022_23960, neoverse_n2, cve_2022_23960

24
lib/cpus/cpu-ops.mk
View file

@ -548,6 +548,10 @@ ERRATA_A710_2216384 ?=0
# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1.
ERRATA_A710_2282622 ?=0
# Flag to apply erratum 2291219 workaround during reset. This erratum applies
# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1.
ERRATA_A710_2291219 ?=0
# Flag to apply erratum 2008768 workaround during reset. This erratum applies
# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1.
ERRATA_A710_2008768 ?=0
@ -592,6 +596,10 @@ ERRATA_N2_2242400 ?=0
# to revision r0p0 of the Neoverse N2 cpu and is still open.
ERRATA_N2_2280757 ?=0
# Flag to apply erraturm 2326639 workaroud during powerdown. This erratum
# applies to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
ERRATA_N2_2326639 ?=0
# Flag to apply erratum 2376738 workaround during reset. This erratum applies
# to revision r0p0 of the Neoverse N2 cpu, it is fixed in r0p1.
ERRATA_N2_2376738 ?=0
@ -635,6 +643,10 @@ ERRATA_X2_2147715 ?=0
# to revision r0p0, r1p0 and r2p0 of the Cortex-X2 cpu and is fixed in r2p1.
ERRATA_X2_2371105 ?=0
# Flag to apply erratum 2313909 workaround on powerdown. This erratum applies
# to revisions r0p0 and r1p0 of the Cortex-X3 cpu, it is fixed in r1p1.
ERRATA_X3_2313909 ?=0
# Flag to apply erratum 1922240 workaround during reset. This erratum applies
# to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1.
ERRATA_A510_1922240 ?=0
@ -1156,6 +1168,10 @@ $(eval $(call add_define,ERRATA_A710_2216384))
$(eval $(call assert_boolean,ERRATA_A710_2282622))
$(eval $(call add_define,ERRATA_A710_2282622))
# Process ERRATA_A710_2291219 flag
$(eval $(call assert_boolean,ERRATA_A710_2291219))
$(eval $(call add_define,ERRATA_A710_2291219))
# Process ERRATA_A710_2008768 flag
$(eval $(call assert_boolean,ERRATA_A710_2008768))
$(eval $(call add_define,ERRATA_A710_2008768))
@ -1200,6 +1216,10 @@ $(eval $(call add_define,ERRATA_N2_2242400))
$(eval $(call assert_boolean,ERRATA_N2_2280757))
$(eval $(call add_define,ERRATA_N2_2280757))
# Process ERRATA_N2_2326639 flag
$(eval $(call assert_boolean,ERRATA_N2_2326639))
$(eval $(call add_define,ERRATA_N2_2326639))
# Process ERRATA_N2_2376738 flag
$(eval $(call assert_boolean,ERRATA_N2_2376738))
$(eval $(call add_define,ERRATA_N2_2376738))
@ -1240,6 +1260,10 @@ $(eval $(call add_define,ERRATA_X2_2147715))
$(eval $(call assert_boolean,ERRATA_X2_2371105))
$(eval $(call add_define,ERRATA_X2_2371105))
# Process ERRATA_X3_2313909 flag
$(eval $(call assert_boolean,ERRATA_X3_2313909))
$(eval $(call add_define,ERRATA_X3_2313909))
# Process ERRATA_A510_1922240 flag
$(eval $(call assert_boolean,ERRATA_A510_1922240))
$(eval $(call add_define,ERRATA_A510_1922240))

5
plat/rpi/common/rpi3_pm.c
View file

@ -187,8 +187,9 @@ static void __dead2 rpi3_pwr_down_wfi(
write_rmr_el3(RMR_EL3_RR_BIT | RMR_EL3_AA64_BIT);
while (1)
;
while (1) {
wfi();
}
}
/*******************************************************************************